Reliability of bond over active pad structures for 0.13-μm CMOS technology

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2003, Pages 1344-1349

  Hess, Kevin J ^a   Downey, Susan H ^a   Hall, Geoffrey B ^a   Lee, Tom ^a   Mercado, Lei L ^a   Miller, James W ^a   Ng, Willson C ^a   Wontor, David G ^a  

^a MOTOROLA INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BONDING; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; RELIABILITY; SEMICONDUCTING SILICON; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DIODES; STRESSES;

BOND OVER ACTIVE PAD STRUCTURES; MULTI-LEVEL METAL WIRING; WIREBONDING;

INTEGRATED CIRCUIT MANUFACTURE;

EID: 0038012272     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (5)

1. Anderson, W., et al, "ESD Protection Under Wire Bonding Pads", 21st Annual EOS/ESD Symposium, 1999, pp. 88-94
2. Heinen, G., et.al. "Wire Bonds Over Active Circuits", 44TH Components & Technology Conference, 1994, pp922-928.
3. Mukai, K., et al. "A New Integration Technology That Enables Forming Bonding Pads On Active Areas", IEEE Proc. IEDM Conf., 1981.
4. Saran, M., et al. "Elimination of Bond-pad Damage Through Structural Reinforcement of Intermetal Dielectrics", IEEE Proc. 36th Annual International Reliability Physics Symposium, 1998, pp225-231.
5. Mercado, L. et al. "Fine Pitch Probing and Wire Bonding and Reliability of Multi-Layer Copper Interconnect Structures", Proc. 33rd Int'l Symp. On Microelectronics, IMAPS, Boston, MA, Sept 2000, pp 727-732.