Content-addressable memory (CAM) circuits and architectures: A tutorial and survey

IEEE Journal of Solid-State Circuits

Volumn 41, Issue 3, 2006, Pages 712-727

  Pagiamtzis, Kostas ^a,b   Sheikholeslami, Ali ^a,b,c  

^a IEEE   (Canada)

^b UNIVERSITY OF TORONTO   (Canada)

^c NONE

Author keywords

Bank selection; Content addressable memory (cam); Matchline pipelining; Matchline sensing; Nand cell; Nor cell; Review; Searchline power

Indexed keywords

BANK SELECTION; CONTENT-ADDRESSABLE MEMORY (CAM); MATCHLINE PIPELINING; MATCHLINE SENSING; NAND CELL; NOR CELL; REVIEW; SEARCHLINE POWER;

COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; PACKET NETWORKS; ROUTERS; TABLE LOOKUP;

COMPUTER CIRCUITS;

EID: 33644661238     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/JSSC.2005.864128     Document Type: Review

References (73)

1. T. Kohonen, Content-Addressable Memories, 2nd ed. New York: Springer-Verlag, 1987.
2. L. Chisvin and R. J. Duckworth, "Content-addressable and associative memory: alternatives to the ubiquitous RAM," IEEE Computer, vol. 22, no. 7, pp. 51-64, Jul. 1989.
3. K. E. Grosspietsch, "Associative processors and memories: a survey," IEEE Micro, vol. 12, no. 3, pp. 12-19, Jun. 1992.
4. I. N. Robinson, "Pattern-addressable memory," IEEE Micro, vol. 12, no. 3, pp. 20-30, Jun. 1992.
5. S. Stas, "Associative processing with CAMs," in Northcon/93 Conf. Record, 1993, pp. 161-167.
6. M. Meribout, T. Ogura, and M. Nakanishi, "On using the CAM concept for parametric curve extraction," IEEE Trans. Image Process., vol. 9, no. 12, pp. 2126-2130, Dec. 2000.
7. M. Nakanishi and T. Ogura, "Real-time CAM-based Hough transform and its performance evaluation," Machine Vision Appl., vol. 12, no. 2, pp. 59-68, Aug. 2000.
8. E. Komoto, T. Homma, and T. Nakamura, "A high-speed and compact-size JPEG Huffman decoder using CAM," in Symp. VLSI Circuits Dig. Tech. Papers, 1993, pp. 37-38.
9. L.-Y. Liu, J.-F. Wang, R.-J. Wang, and J.-Y. Lee, "CAM-based VLSI architectures for dynamic Huffman coding," IEEE Trans. Consumer Election., vol. 40, no. 3, pp. 282-289, Aug. 1994.
10. B. W. Wei, R. Tarver, J.-S. Kim, and K. Ng, "A single chip Lempel-Ziv data compressor," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), vol. 3, 1993, pp. 1953-1955.
11. R.-Y. Yang and C.-Y. Lee, "High-throughput data compressor designs using content addressable memory," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), vol. 4, 1994, pp. 147-150.
12. C.-Y. Lee and R.-Y. Yang, "High-throughput data compressor designs using content addressable memory," IEE Proc. - Circuits, Devices and Syst., vol. 142, no. 1, pp. 69-73, Feb. 1995.
13. D. J. Craft, "A fast hardware data compression algorithm and some algorithmic extansions," IBM J. Res. Devel., vol. 42, no. 6, pp. 733-745, Nov. 1998.
14. S. Panchanathan and M. Goldberg, "A content-addressable memory architecture for image coding using vector quantization," IEEE Trans. Signal Process., vol. 39, no. 9, pp. 2066-2078, Sep. 1991.
15. T.-B. Pei and C. Zukowski, "VLSI implementation of routing tables: tries and CAMs," in Proc. IEEE INFOCOM, vol. 2, 1991, pp. 515-524.
16. _, "Putting routing tables in silicon," IEEE Network Mag., vol. 6, no. 1, pp. 42-50, Jan. 1992.
17. A. J. McAuley and P. Francis, "Fast routing table lookup using CAMs," in Proc. IEEE INFOCOM, vol. 3, 1993, pp. 1282-1391.
18. N.-F. Huang, W.-E. Chen, J.-Y. Luo, and J.-M. Chen, "Design of multi-field IPv6 packet classifiers using ternary CAMs," in Proc. IEEE GLOBECOM, vol. 3, 2001, pp. 1877-1881.
19. G. Qin, S. Ata, I. Oka, and C. Fujiwara, "Effective bit selection methods for improving performance of packet classifications on IP routers," in Proc. IEEE GLOBECOM, vol. 2, 2002, pp. 2350-2354.
20. H. J. Chao, "Next generation routers," Proc. IEEE, vol. 90, no. 9, pp. 1518-1558, Sep. 2002.
21. G. Kasai, Y. Takarabe, K. Furumi, and M. Yoneda, "200 MHz/200 MSPS 3.2 W at 1.5 V Vdd, 9.4 Mbits ternary CAM with new charge injection match detect circuits and bank selection scheme," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2003, pp. 387-390.
22. A. Roth, D. Foss, R. McKenzie, and D. Perry, "Advanced ternary CAM circuits on 0.13 μm logic process technology," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2004, pp. 465-468.
23. T. Yamagato, M. Mihara, T. Hamamoto, Y. Murai, T. Kobayashi, M. Yamada, and H. Ozaki, "A 288-kbit fully parallel content addressable memory using a stacked-capacitor cell structure," IEEE J. Solid-State Circuits, vol. 27, no. 12, pp. 1927-1933, Dec. 1992.
24. T. Ogura, M. Nakanishi, T. Baba, Y. Nakabayashi, and R. Kasai, "A 336-kbit content addressable memory for highly parallel image processing," in Proc. IEEE Custom Integmted Circuits Conf. (CICC), 1996, pp. 273-276.
25. H. Kadota, J. Miyake, Y. Nishimichi, H. Kudoh, and K. Kagawa, "An 8-kbit content-addressable and reentrant memory," IEEE J. Solid-State Circuits, vol. SC-20, no. 5, pp. 951-957, Oct. 1985.
26. K. J. Schultz, F. Shafai, G. F. R. Gibson, A. G. Bluschke, and D. E. Somppi, "Fully parallel 25 MHz, 2.5-Mb CAM," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 1998, pp. 332-333.
27. V. Lines, A. Ahmed, P. Ma, and S. Ma, "66 MHz 2.3 M ternary dynamic content addressable memory," in Record IEEE Int. Workshop on Memory Technology, Design and Testing, 2000, pp. 101-105.
28. R. Panigrahy and S. Sharma, "Sorting and searching using ternary CAMs," in Proc. Symp. High Performance. Interconnects, 2002, pp. 101-106.
29. _, "Sorting and searching using ternary CAMs," IEEE Micro, vol. 23, no. 1, pp. 44-53, Jan.-Feb. 2003.
30. H. Noda, K. Inoue, M. Kuroiwa, F. Igaue, K. Yamamoto, H. J. Mattausch, T. Koide, A. Amo, A. Hachisuka, S. Soeda, I. Hayashi, F. Morishita, K. Dosaka, K. Arimoto, K. Fujishima, K. Anami, and T. Yoshihara, "A cost-efficient high-performance dynamic TCAM with pipelined hierarchical search and shift redudancy architecture," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 245-253, Jan. 2005.
31. S. R. Ramírez-Chávez, "Encoding don't cares in static and dynamic content-addressable memories," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 39, no. 8, pp. 575-578, Aug. 1992.
32. S. Choi, K. Sohn, M.-W. Lee, S. Kim, H.-M. Choi, D. Kim, U.-R. Cho, H.-G. Byun, Y.-S. Shin, and H.-J. Yoo, "A 0.7 fJ/bit/search, 2.2ns search time hybrid type TCAM architecture," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2004, pp. 498-199.
33. S. Choi, K. Sohn, and H.-J. Yoo, "A 0.7 fJ/bit/search, 2.2-ns search time hybrid-type TCAM architecture," IEEE J. Solid-State Circuits, vol. 40, no. 1, pp. 254-260, Jan. 2005.
34. H. Miyatake, M. Tanaka, and Y. Mori, "A design for high-speed low-power CMOS fully parallel content-addressable memory macros," IEEE J. Solid-State Circuits, vol. 36, no. 6, pp. 956-968, Jun. 2001.
35. S. Liu, F. Wu, and J. B. Kuo, "A novel low-voltage content-addressable memory (CAM) cell with a fast tag-compare capability using partially depleted (PD) SOI CMOS dynamic-threshold (DTMOS) techniques," IEEE J. Solid-State Circuits, vol. 36, no. 4, pp. 712-716, Apr. 2001.
36. G. Thirugnanam, N. Vijaykrishnan, and M. J. Irwin, "A novel low power CAM design," in Proc. 14th Annu. IEEE ASIC/SOC Conf., 2001, pp. 198-202.
37. K. J. Schultz, "Content-addressable memory core cells: a survey," Integration, VLSI J., vol. 23, no. 2, pp. 171-188, Nov. 1997.
38. J.-S. Wang, H.-Y. Li, C.-C. Chen, and C. Yeh, "An AND-type match-line scheme for energy-efficient content addressable memories," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2005, pp. 464-465.
39. F. Shafai, K. J. Schultz, G. F. R. Gibson, A. G. Bluschke, and D. E. Somppi, "Fully parallel 30-MHz, 2.5-Mb CAM," IEEE J. Solid-State Circuits, vol. 33, no. 11, pp. 1690-1696, Nov. 1998.
40. B. S. Amrutur and M. A. Horowitz, "A replica technique for wordline and sense control in low-power SRAMs," IEEE J. Solid-State Circuits, vol. 33, no. 8, pp. 1208-1219, Aug. 1998.
41. M. M. Khellah and M. Elmasry, "Use of charge sharing to reduce energy consumption in wide fan-in gates," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), vol. 2, 1998, pp. 9-12.
42. I. Arsovski, T. Chandler, and A. Sheikholeslami, "A ternary content-addressable memory (TCAM) based on 4T static storage and including a current-race sensing scheme," IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 155-158, Jan. 2003.
43. C. A. Zukowski and S.-Y. Wang, "Use of selective precharge for low-power content-addressable memories," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), vol. 3, 1997, pp. 1788-1791.
44. I. Y.-L. Hsiao, D.-H. Wang, and C.-W. Jen, "Power modeling and low-power design of content addressable memories," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), vol. 4, 2001, pp. 926-929.
45. A. Efthymiou and J. D. Garside, "An adaptive serial-parallel CAM architecture for low-power cache blocks," in Proc. IEEE Int. Symp. Low Power Electronics and Design (ISLPED), 2002, pp. 136-141.
46. _, "A CAM with mixed serial-parallel comparison for use in low energy caches," IEEE Trans. VLSI Syst., vol. 12, no. 3, pp. 325-329, Mar. 2004.
47. N. Mohan and M. Sachdev, "Low power dual matchline content addressable memory," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), vol. 2, 2004, pp. 633-636.
48. K.-H. Cheng, C.-H. Wei, and S.-Y. Jiang, "Static divided word matchline line for low-power content addressable memory design," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), vol. 2, 2004, pp. 629-632.
49. K. Pagiamtzis and A. Sheikholeslami, "Pipelined match-lines and hierarchical search-lines for low-power content-addressable memories," in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2003, pp. 383-386.
50. _, "A low-power content-addressable memory (CAM) using pipelined hierarchical search scheme," IEEE J. Solid-State Circuits, vol. 39, no. 9, pp. 1512-1519, Sep. 2004.
51. J. M. Hyjazie and C. Wang, "An approach for improving the speed of content addressable memories," in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), vol. 5, 2003, pp. 177-180.
52. I. Arsovski and A. Sheikholeslami, "A current-saving match-line sensing scheme for content-addressable memories," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2003, pp. 304-305.
53. _, "A mismatch-dependent power allocation technique for match-line sensing in content-addressable memories," IEEE J. Solid-State Circuits, vol. 38, no. 11, pp. 1958-1966, Nov. 2003.
54. P.-F. Lin and J. B. Kuo, "A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme," IEEE J. Solid-State Circuits, vol. 37, no. 10, pp. 1307-1317, Oct. 2002.
55. J. M. Rabaey, A. Chandrakasan, and B. Nikolíc, Digital Integrated Circuits: A Design Perspective, 2nd ed. Englewood Cliffs, NJ: Prentice-Hall, 2003.
56. H. Noda, K. Inoue, M. Kuroiwa, A. Amo, A. Hachisuka, H. J. Mattausch, T. Koide, S. Soeda, K. Dosaka, and K. Arimoto, "A 143 MHz 1.1 W 4.5 Mb dynamic TCAM with hierarchical searching and shift redundancy architecture," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2004, pp. 208-209.
57. K. J. Schultz and P. G. Gulak, "Architectures for large-capacity CAMs," Integration, VLSI J., vol. 18, no. 2-3, pp. 151-171, Jun. 1995.
58. M. Motomura, J. Toyoura, K. Hirata, H. Ooka, H. Yamada, and T. Enomoto, "A 1.2-million transistor, 33-MHz, 20-bit dictionary search processor with a 160 kb CAM," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 1990, pp. 90-91.
59. _, "A 1.2-million transistor, 33-MHz, 20-b dictionary search processor (DISP) with a 160-kb CAM," IEEE J. Solid-State Circuits, vol. 25, no. 5, pp. 1158-1165, Oct. 1990.
60. K. J. Schultz and P. G. Gulak, "Fully parallel multi-megabit integrated CAM/RAM design," in Records IEEE Int. Workshop on Memory Technology, Design and Testing, 1994, pp. 46-51.
61. _, "Fully parallel integrated CAM/RAM using preclassification to enable large capacities," IEEE J. Solid-State Circuits, vol. 31, no. 5, pp. 689-699, May 1996.
62. R. Panigrahy and S. Sharma, "Reducing TCAM power consumption and increasing throughput," in Proc. Symp. High Performance. Interconnects, 2002, pp. 107-112.
63. F. Zane, G. Narlikar, and A. Basu, "CoolCAMs: power-efficient TCAMs for forwarding engines," in Proc. IEEE INFOCOM, vol. 1, 2003, pp. 42-52.
64. C.-S. Lin, J.-C. Chang, and B.-D. Liu, "Design for low-power, low-cost, and high-reliability precomputation-based content-addressable memory," in Proc. Asia-Pacific Conf. Circuits Syst., vol. 2, 2002, pp. 319-324.
65. _, "A low-power precomputation-based fully parallel content-addressable memory," IEEE J. Solid-State Circuits, vol. 38, no. 4, pp. 654-662, Apr. 2003.
66. S. Hanzawa, T. Sakata, K. Kajigaya, R. Takemura, and T. Kawahara, "A dynamic CAM - based on a one-hot-spot block code-for millions-entry lookup," in Symp. VLSI Circuits Dig. Tech. Papers, 2004, pp. 382-385.
67. _, "A large-scale and low-power CAM architecture featuring a one-hot-spot block code for IP-address lookup in a network router," IEEE J. Solid-State Circuits, vol. 40, no. 4, pp. 853-861, Apr. 2005.
68. H. Liu, "Efficient mapping of range classifier into ternary-CAM," in Proc. Symp. High Performance Interconnects, 2001, pp. 95-100.
69. _, "Routing table compaction in ternary cam," IEEE Micro, vol. 22, no. 1, pp. 58-64, Jan.-Feb. 2002.
70. V. Ravikumar and R. N. Mahapatra, "TCAM architecture for IP lookup using prefix properties," IEEE Micro, vol. 24, no. 2, pp. 60-69, Mar.-Apr. 2004.
71. A. Sheikholeslami and P. G. Gulak, "A survey of circuit innovations in ferroelectric random-access memories," Proc. IEEE, vol. 88, no. 5, pp. 677-689, May 2000.
72. S. Tehrani, J. M. Slaughter, M. DeHerrera, B. N. Engel, N. D. Rizzo, J. Salter, M. Durlam, R. W. Dave, J. Janesky, B. Butcher, K. Smith, and G. Grynkewich, "Magnetoresistive random access memory using magnetic tunnel junctions," Proc. IEEE, vol. 91, no. 5, pp. 703-714, May 2003.
73. K. Kim and G. Jeong, "Memory technologies in the nano-era: challenges and opportunities," in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, 2005, pp. 576-577.