Detecting signal-overshoots for reliability analysis in high-speed system-on-chips

IEEE Transactions on Reliability

Volumn 51, Issue 4, 2002, Pages 494-504

  Nourani, Mehrdad ^a,b   Attarha, Amir R ^b  

^a IEEE   (United States)

^b UNIVERSITY OF TEXAS AT DALLAS   (United States)

Author keywords

High speed interconnect; Hot carrier; Reliability loss; System on chip; Voltage overshoot

Indexed keywords

HIGH-SPEED INTERCONNECT; HIGH-SPEED SYSTEM-ON-CHIPS; RELIABILITY LOSS; VOLTAGE OVERSHOOT;

CMOS INTEGRATED CIRCUITS; DYNAMIC RANDOM ACCESS STORAGE; ELECTRIC POTENTIAL; FLIP FLOP CIRCUITS; HOT CARRIERS; INTEGRATED CIRCUIT MANUFACTURE; INTEGRATED CIRCUIT TESTING; INTERCONNECTION NETWORKS; VLSI CIRCUITS;

RELIABILITY;

EID: 0036890592     PISSN: 00189529     EISSN: None     Source Type: Journal    
DOI: 10.1109/TR.2002.804491     Document Type: Article

References (36)

1. Semiconductor Industry Association, The National Technology Roadmap for Semiconductors: Sematech, Inc, 1997.
2. R. Chandramouli and S. Pateras, "Testing systems on a chip," IEEE Spectrum, pp. 42-47, 1996.
3. Y. Leblebici, "Design considerations for CMOS digital circuits with improved hot-carrier reliability," IEEE J. Solid-State Circuits, vol. 31, pp. 1014-1024, 1996.
4. J. Brews, "Overshoot controlled RLC interconnections," IEEE Trans. Electron Devices, vol. 38, pp. 76-87, 1991.
5. S. Kundu and U. Ghoshal, "Inductance analysis of on-chip interconnects," in Proc. European Design & Test Conference (EDTC), 1997, pp. 252-255.
6. K. Mistry, R. Hokinson, and B. Gieseke et al., "Voltage overshoots and N-MOSFET hot carrier robustness in VLSI circuits," in IEEE Reliability Phys. Symp., 1994, pp. 65-71.
7. V. Chan, T. Kopley P. Marcoux, and J. Chung, "High frequency AC hot-carrier degradation in CMOS circuits," in Proc. IEEE Int. Meeting on Electron Devices, 1994, pp. 11.3.1-11.3.4.
8. J. F. Chen, J. Tao, P. Fang, and C. Hu, "Performance and reliability comparison between asymmetric and symmetric LDD devices and logic gates," IEEE J. Solid-State Circuits, vol. 34, pp. 367-371, 1999.
9. W. Weber, M. Brox, and T. Kunemund et al., "Dynamic degradation in MOSFETs-Part II: Application in the circuit environment," IEEE Trans. Electron Devices, vol. 38, pp. 1859-1867, 1991.
10. d model for hot carrier reliability simulation," in IEEE 37th Annu. Int. Reliability Phys. Symp., 1999, pp. 243-248.
11. P. Fang, J. Tao, J. Chen, and C. Hu, "Design in hot carrier reliability for high performance logic applications," in Proc. IEEE Custom Integrated Circuits Conf., 1998, pp. 25.1.1-25.1.7.
12. P. Fang, P. Li, and J. Yue, "Circuit hot carrier reliability simulation in advanced CMOS process technology development," IEEE Integrity Reliability Workshop, Final Report, pp. 73-78, 1994.
13. W. Jiang, H. Le, and J. Chung et al., "Assessing circuit-level hot-carrier reliability," in Proc. IEEE 36th Annu. Int. Reliability Phys. Symp., 1998, pp. 173-179.
14. A. Sinha, S. Gupta, and M. Breuer, "Validation and test generation for oscillatory noise in VLSI interconnects," in Proc. Int. Conf. Computer Aided Design (ICCAD-1999), 1999, pp. 289-296.
15. P. Nordholz, D. Treytnar, and J. Otterstedt et al., "Signal integrity problems in deep submicron arising from interconnects between cores," in Proc. VLSI Test Symp. (VTS-1998), 1998, pp. 28-33.
16. P. Chen and K. Keutzer, "Toward true crosstalk noise analysis," in Proc. Int. Conf. Computer Aided Design (ICCAD-1999), 1999, pp. 132-137.
17. W. Chen, S. Gupta, and M. Breuer, "Test generation in VLSI circuits for crosstalk noise," in Proc. Int. Test Conf. (ITC-1998), 1998, pp. 641-650.
18. K. Lee, C. Nordquist, and J. Abraham, "Automatic test pattern generation for crosstalk glitches in digital circuits," in Proc. VLSI Test Symp. (VTS-1998), 1998, pp. 34-39.
19. M. Cuviello, S. Dey, X. Bai, and Y. Zhao, "Fault modeling and simulation for crosstalk in system-on-chip interconnects," in Proc. Int. Conf. Computer Aided Design (ICCAD-1999), 1999, pp. 297-303.
20. D. K. Nayak, M. Hao, J. Umali, and R. Rakkhit, "A comprehensive study of performance and reliability of P, As, and hybrid As/P nLDD junctions for deep-submicron CMOS logic technology," IEEE Electron Device Lett., vol. 18, pp. 281-283, 1997.
21. R. Tu, E. Rosenbaum, and W. Chan et al., "Berkeley reliability tools-BERT," IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol. 12, pp. 1524-1534, 1993.
22. K. Gala, V. Zolotov, and R. Panda et al., "On-chip inductance modeling and analysis," in Proc. Design Automation Conf. (DAC-2000), 2000, pp. 63-68.
23. B. Sheehan, "Projective convolution: RLC model-order reduction using the impulse response," in Proc. Design Automation Conf. (DAC-1999), 1999, pp. 669-673.
24. M. Silveira, M. Kamon, I. Elfadel, and J. White, "A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits," in Proc. Design Automation Conf. (DAC-1996), 1996, pp. 288-924.
25. C. Cheng, J. Lillis, S. Lin, and N. Chang, Interconnect Analysis and Synthesis: John Wiley & Sons, 2000.
26. H. Veendrick, Deep-Submicron CMOS ICs: From Basics to Asics: Kluwer, 1998.
27. CODAC User's and Reference Manual: Texas Instrument Inc., 2000.
28. TI SPICE3 User's and Reference Manual: Texas Instrument Inc., 2000.
29. J. Rabaey, Digital Integrated Circuits: Prentice Hall, 1996.
30. P. Gray and R. Meyer, Analysis and Design of Analog Integrated Circuits: John Wiley & Sons, 1993.
31. P. Allen and D. Holberg, CMOS Analog Circuit Design: Oxford Univ. Press, 1987.
32. M. Elrabaa, I. Abu-Khater, and M. Elmasry, Advanced Low-Power Digital Circuit Techniques: Kluwer Academic, 1997.
33. Intel Corporation, "MCS-51 8-bit microcontroller", Databook of Intel MCS-51 Microcontroller, 1994.
34. Synopsys Design Analyzer, User Manuals for SYNOPSYS Toolset Version 2000.05-1: Synopsys Inc., 2000.
35. J. Devorce, Probability and Statistics for Engineering and the Sciences: John Wiley & Sons, 1999.
36. MOSIS Organization, USC Information Sciences Institute [Online]. Available: http://www.mosis.org.