Vertical profile optimisation of a self-aligned SiGeC HBT process with an n-Cap emitter

Proceedings of the IEEE Bipolar/BiCMOS Circuits and Technology Meeting

Volumn , Issue , 2003, Pages 111-114

  Donkers, J J T M ^a   Magnee P H C ^a   Huizing, H G A ^a   Agarwal, P ^a   Aksen, E ^a   Meunier Beillard, P ^a,b   Neuilly, F ^a,b   Havens, R J ^a   Vanhoucke, T ^a  

^a PHILIPS RESEARCH LABORATORIES   (Netherlands)

^b IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC BREAKDOWN; EPITAXIAL GROWTH; GATES (TRANSISTOR); OPTIMIZATION; SEMICONDUCTING BORON; SEMICONDUCTING SILICON COMPOUNDS; SEMICONDUCTOR DEVICE STRUCTURES; SEMICONDUCTOR DOPING; SEMICONDUCTOR JUNCTIONS;

CAP EMITTER; PROCESS INTEGRATION; SEMICONDUCTING SILICON GERMANIUM CARBIDE; VERTICAL PROFILE OPTIMISATION;

HETEROJUNCTION BIPOLAR TRANSISTORS;

EID: 1042277546     PISSN: 10889299     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/bipol.2003.1274947     Document Type: Conference Paper

References (7)

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7. L. C. M. van den Oever et al., "Design of 200 GHz SiGe HBT's", Proc. BCTM, pp. 78-81, 2001.