Nanometer MOSFET variation in minimum energy subthreshold circuits

IEEE Transactions on Electron Devices

Volumn 55, Issue 1, 2008, Pages 163-174

  Verma, Naveen ^a   Kwong, Joyce ^a   Chandrakasan, Anantha P ^a  

^a MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

CMOS digital integrated circuits; Leakage currents; Logic design; Low power electronics; Matching; Static random access memory (SRAM); Subthreshold; Yield estimation

Indexed keywords

DIGITAL INTEGRATED CIRCUITS; ELECTRIC NETWORK TOPOLOGY; ENERGY EFFICIENCY; ESTIMATION; LEAKAGE CURRENTS; LOGIC DESIGN; STATIC RANDOM ACCESS STORAGE; THRESHOLD VOLTAGE;

NANOMETER; SUBTHRESHOLD CIRCUITS; YIELD ESTIMATION;

MOSFET DEVICES;

EID: 37749025732     PISSN: 00189383     EISSN: None     Source Type: Journal    
DOI: 10.1109/TED.2007.911352     Document Type: Article

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