High-k/metal gate stacks in gate first and replacement gate schemes

ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings

Volumn , Issue , 2010, Pages 256-259

  Kesapragada, Sree ^a   Wang, Rongjun ^a   Liu, Dave ^a   Liu, Guojun ^a   Xie, Zhigang ^a   Ge, Zhenbin ^a   Yang, Haichun ^a   Lei, Yu ^a   Lu, Xinliang ^a   Tang, Xianmin ^a   Lei, Jianxin ^a   Allen, Miller ^a   Gandikota, Srinivas ^a   Moraes, Kevin ^a   Hung, Steven ^a   Yoshida, Naomi ^a   Chang, Chorng Ping ^a  

^a APPLIED MATERIALS INC   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CAP LAYERS; GATE FIRST; GATE STACKS; GATE TRENCHES; INTEGRATION SCHEME; SUBSTRATE MODIFICATIONS; TIN METAL GATE; VOID-FREE;

MANUFACTURE; SEMICONDUCTOR GROWTH; STOICHIOMETRY; TITANIUM NITRIDE;

ALUMINUM;

EID: 77957581457     PISSN: 10788743     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ASMC.2010.5551460     Document Type: Conference Paper

References (15)

1. S. Guha et. al. Appl. Phys. Lett. 77, p2710, 2000.
2. V. Narayanan et. al. VLSI Symp. Tech. Dig. P178, 2006.
3. X.P. Wang, et. al. IEEE Elec. Dev. Lett. 27, p31, 2006.
4. H.N. Alshareef et. al. Appl. Phys. Lett. 89, p232103, 2006.
5. S. Guha et. al. Appl. Phys. Lett. 90, p092902, 2007.
6. Y. Tateshita et. al. IEDM, p63, 2006.
7. S. Mayuzumi et. al. IEM, p293, 2007.
8. J. Wang et. al. VLSI Sym. Tech. Dig. p46, 2007.
9. C. Auth et. al. VLSI Sym. Tech. Dig. p128, 2008.
10. K. Mistry et. al. IEDM, p247, 2007.
11. P. Sivasubramani et. al. VLSI, p68, 2007.
12. H.C. Wen et. al. VLSI, p160, 2007.
13. H. Harris et. al. IRPS, p661, 2006.
14. Y. Liu et. al. Jap. J. Appl. Phys. 47 p2433, 2008.
15. J. Westlinder et. al. Microelec. Eng. 75 p389, 2004.