Methods for fault tolerance in networks-on-chip

ACM Computing Surveys

Volumn 46, Issue 1, 2013, Pages

  Radetzki, Martin ^a   Feng, Chaochao ^b   Zhao, Xueqian ^c   Jantsch, Axel ^c  

^a UNIVERSITY OF STUTTGART   (Germany)

^b NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY   (China)

^c ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

Dependability; Diagnosis; Failure mechanisms; Fault models; Fault tolerance; Network on Chip; Reconfiguration

Indexed keywords

DEPENDABILITY; FAILURE MECHANISM; FAULT MODEL; NETWORK ON CHIP; RECONFIGURATION;

DIAGNOSIS; FAILURE (MECHANICAL); MICROPROCESSOR CHIPS; NETWORK LAYERS; REDUNDANCY; RESEARCH; VLSI CIRCUITS;

FAULT TOLERANCE;

EID: 84887417271     PISSN: 03600300     EISSN: 15577341     Source Type: Journal    
DOI: 10.1145/2522968.2522976     Document Type: Article

References (162)

1. AGARWAL,M.,PAUL, B.,ZHANG,M., ANDMITRA, S. 2007. Circuit failure prediction and its application to transistor aging. In Proceedings of the 25th IEEE VLSI Test Symposium. 277-286.
2. AISOPOS, K., CHEN, C.-H., AND PEH, L.-S. 2011a. Enabling system-level modeling of variation-induced faults in networks-on-chips. In Proceedings of the 48th ACM/EDAC/IEEE Design Automation Conference (DAC11). 930-935.
3. AISOPOS, K.,DEORIO, A.,PEH, L.-S., AND BERTACCO, V. 2011b. Ariadne: Agnostic reconfiguration in a disconnected network environment. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT11). 298-309.
4. ALAGHI, A., KARIMI, N., SEDGHI, M., AND NAVABI, Z. 2007. Online noc switch fault detection and diagnosis using a high level fault model. In Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT07). 21-29.
5. ALAGHI, A., SEDGHI, M.,KARIMI, N., FATHY, M., AND NAVABI, Z. 2008. Reliable noc architecture utilizing a robust rerouting algorithms. In 9th IEEE East-West Design and Test Symposium (EWDTS08).
6. ALI, M.,WELZL, M., AND HELLEBRAND, S. 2005. A dynamic routing mechanism for network on chip. In Proceedings of the 23rd NORCHIP Conference. 70-73.
7. ALI, M., WELZL, M., AND HESSLER, S. 2007. And end 2 end reliability protocol to address transient faults in network on chips. In Digest of the Workshop on Diagnostic Services in Network-on-Chips.
8. ANGHEL, L. AND NICOLAIDIS, M. 2000. Cost reduction and evaluation of a temporary faults detecting technique. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition. 591-598.
9. ANGIOLINI, F., MELONI, P., CARTA, S., BENINI, L., AND RAFFO, L. 2006. Contrasting a noc and a traditional interconnect fabric with layout awareness. In Proceedings of the Conference on Design, Automation and Test in Europe (DATE06). Vol. 1. 1-6.
10. AVIZIENIS, A., LAPRIE, J.-C., RANDELL, B., AND LANDWEHR, C. 2004. Basic concepts and taxonomy of dependable and secure Computing. IEEE Trans. Dependable Secure Comput. 1, 1, 11-33.
11. BAUMANN, R. 2005. Soft errors in advanced computer systems. IEEE Des. Test Comput. 22, 3, 258-266.
12. BELL, S., EDWARDS, B., AMANN, J., CONLIN, R., JOYCE, K., LEUNG, V., MACKAY, J., REIF, M., BAO, L., BROWN, J., MATTINA, M., MIAO, C.-C., RAMEY, C., WENTZLAFF, D., ANDERSON, W., BERGER, E., FAIRBANKS, N., KHAN, D., MONTENEGRO, F.,STICKNEY, J., AND ZOOK, J. 2008. TILE64 processor: A 64-core SoC withmesh interconnect. In Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC08). 87-90.
13. BERTOZZI, D., BENINI, L., AND DE MICHELI, G. 2002. Low power error resilient encoding for on-chip data buses. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition. 102-109.
14. BERTOZZI, D., BENINI, L., AND DE MICHELI, G. 2005. Error control schemes for on-chip communication links: The energy reliability tradeoff. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 24, 6, 818-831.
15. BJERREGAARD, T. ANDMAHADEVAN, S. 2006. A survey of research and practices of network-on-chip. ACMComput. Surv. 38, 1-51.
16. BOBDA, C.,AHMADINIA, A.,MAJER, M.,TEICH, J.,FEKETE, S., AND VAN DER VEEN, J. 2005. Dynoc: A dynamic infrastructure for communication in dynamically reconfigurable devices. In Proceedings of the International Field Programmable Logic and Applications Conference. 153-158.
17. BOGDAN, P., DUMITRAS, T., AND MARCULESCU, R. 2007. Stochastic communication: A new paradigm for faulttolerant networks-on-chip. VLSI Des. 2007, 1-17.
18. BOLOTIN, E.,CIDON, I.,GINOSAR, R., AND KOLODNY, A. 2007. Routing table minimization for irregular mesh nocs. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE07). 1-6.
19. BONDAVALLI, A., CHIARADONNA, S., GIANDOMENICO, F. D., AND GRANDONI, F. 2000. Threshold-based mechanisms to discriminate transient from intermittent faults. IEEE Trans. Comput. 49, 4, 230-245.
20. BOPPANA, R. V. AND CHALASANI, S. 1995. Fault-tolerant wormhole routing algorithms for mesh networks. IEEE Trans. Comput. 44, 7, 848-864.
21. BORKAR, S. 2005. Designing reliable systems from unreliable components: The challenges of transistor variability and degradation. IEEE Micro 25, 6, 10-16.
22. BORKAR, S. 2007. Thousand core chips: A technology perspective. In Proceedings of the 44th Annual Design Automation Conference (DAC07). ACM Press, New York, 746-749.
23. BOYAN, J. AND LITTMAN, M. 1994. Packet routing in dynamically changing networks: A reinforcement learning approach. Adv. Neural Inf. Process. Syst. 6, 671-678.
24. BREUER, M., GUPTA, S., AND MAK, T. 2004. Defect and error tolerance in the presence of massive numbers of defects. IEEE Des. Test Comput. 21, 3, 216-227.
25. CHEN, C.-L. AND CHIU, G.-M. 2001. A fault-tolerant routing scheme for meshes with nonconvex faults. IEEE Trans. Parallel Distrib. Syst. 12, 5, 467-475.
26. CONCATTO, C.,MATOS, D., CARRO, L., KASTENSMIDT, F., SUSIN, A., COTA, E., AND KREUTZ, M. 2009. Fault tolerant mechanism to improve yield in nocs using a reconfigurable router. In Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design (SBCCI09). ACM Press, New York, 1-6.
27. CONSTANTINESCU, C. 2003. Trends and challenges in vlsi circuit reliability. IEEE Micro 23, 4, 14-19.
28. CONSTANTINIDES, K., PLAZA, S., BLOME, J., ZHANG, B., BERTACCO, V., MAHLKE S., AUSTIN, T., AND ORSHANSKY, M. 2006. Bulletproof: A defect-tolerant cmp switch architecture. In Proceedings of the 12th International High-Performance Computer Architecture Symposium. 5-16.
29. COTA, E., KASTENSMIDT, F., CASSEL, M., HERVE, M., ALMEIDA, P., MEIRELLES, P., AMORY, A., AND LUBASZEWSKI, M. 2008. A high-fault-coverage approach for the test of data, control and handshake interconnects in mesh networks-on-chip. IEEE Trans. Comput. 57, 9, 1202-1215.
30. CUVIELLO, M., DEY, S., BAI, X., AND ZHAO, Y. 1999. Fault modeling and simulation for crosstalk in system-onchip interconnects. In IEEE/ACM International Digest of Technical Papers on Computer-Aided Design. 297-303.
31. DALIRSANI, A., HOLST, S., ELM, M., AND WUNDERLICH, H. 2011. Structural test for graceful degradation of noc switches. In Proceedings of the European Test Symposium (ETS11). 183-188.
32. DEMICHELI, G. AND BENINI, L. 2006. Networks On Chips: Technology and Tools.Morgan Kaufmann Publishers.
33. DODD, P. AND MASSENGILL, L. 2003. Basic mechanisms and modeling of single-event upset in digital microelectronics. IEEE Trans. Nuclear Sci. 50, 3, 583-602.
34. DUAN, X., ZHANG, D., AND SUN, X. 2009. Fault-tolerant routing schemes for wormhole mesh. In Proceedings of the IEEE International Parallel and Distributed Processing with Applications Symposium. 298-301.
35. DUATO, J., LYSNE, O., PANG, R., AND PINKSTON, T. 2005. Part i: A theory for deadlock-free dynamic network reconfiguration. IEEE Trans. Parallel Distrib. Syst. 16, 5, 412-427.
36. DUBROVA, E. 2008. Fault-Tolerant Design: An Introduction. Kluwer Academic Publishers.
37. DUMITRAS, T. AND MARCULESCU, R. 2003. On-chip stochastic communication [soc applications]. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE03). 790-795.
38. DUTTA, A. AND TOUBA, N. 2007. Reliable network-on-chip using a low cost unequal error protection code. In Proceedings of the 22nd IEEE International Defect and Fault-Tolerance in VLSI Systems Symposium (DFT07). 3-11.
39. EGHBAL, A., YAGHINI, P. M., PEDRAM, H., AND ZARANDI, H. R. 2010. Designing fault-tolerant network-on-chip router architecture. Int. J. Electron. 97, 10, 1181-1192.
40. EJLALI, A., AL-HASHIMI, B. M., ROSINGER, P., AND MIREMADI, S. G. 2007. Joint consideration of fault-tolerance, energy efficiency and performance in on-chip networks. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE07). 647-1652.
41. ELAKKUMANAN, P., PRASAD, K., AND SRIDHAR, R. 2006. Time redundancy based scan flip-flop reuse to reduce ser of combinational logic. In Proceedings of the 7th International Symposium on Quality Electronic Design (ISQED06). IEEE Computer Society, Los Alamitos, CA, 617-624.
42. ERNST, D., KIM, N. S., DAS, S., PANT, S., RAO, R., PHAM, T., ZIESLER, C., BLAAUW, D., AUSTIN, T., FLAUTNER, K., AND MUDGE, T. 2003. Razor: A low-power pipeline based on circuit-level timing speculation. In Proceedings of the 36th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO03). 7-18.
43. FENG, C., LU, Z., JANTSCH, A., LI, J., AND ZHANG, M. 2010a. FoN: Fault-on-neighbor aware routing algorithm for networks-onchip. In International SOC Conference.
44. FENG, C., LU, Z., JANTSCH, A., LI, J., AND ZHANG, M. 2010b. A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for networks-on-chip. In Proceedings of the International Workshop on Network on Chip Architectures (NoCArc10).
45. FICK, D., DEORIO, A., CHEN, G., BERTACCO, V., SYLVESTER, D., AND BLAAUW, D. 2009a. A highly resilient routing algorithm for fault-tolerant nocs. In Proceedings of theDesign, Automation and Test in Europe Conference and Exhibition (DATE09). 21-26.
46. FICK, D., DEORIO, A., HU, J., BERTACCO, V., BLAAUW, D., AND SYLVESTER, D. 2009b. Vicis: A reliable network for unreliable silicon. In Proceedings of the 46th Annual Design Automation Conference (DAC09). ACM Press, New York, 812-817.
47. FIORIN, L.,MICCONI, L., AND SAMI,M. 2011. Design of fault tolerant network interfaces for nocs. In Proceedings of the 14th Euromicro Conference on Digital System Design. 393-400.
48. FLICH, J., MEJIA, A., LOPEZ, P., AND DUATO, J. 2007. Region-based routing: An efficient routing mechanism to tackle unreliable hardware in network on chips. In Proceedings of the Symposium on Networks-on-Chip (NOCS07). 183-194.
49. FLICH, J., SKEIE, T.,MEJIA, A., LYSNE, O., LOPEZ, P., ROBLES, A.,DUATO, J.,KOIBUCHI, M., ROKICKI, T., AND SANCHO, J. 2012. A survey and evaluation of topology-agnostic deterministic routing algorithms. IEEE Trans. Parallel Distrib. Syst. 23, 3, 405-425.
50. FORNEY, G. D. 1973. The viterbi algorithm. Proc. IEEE 61, 3, 268-278.
51. FRANTZ, A.,KASTENSMIDT, F., CARRO, L., AND COTA, E. 2006a. Dependable network-on-chip router able to simultaneously tolerate soft errors and crosstalk. In Proceedings of the IEEE International Test Conference (ITC06). 1-9.
52. FRANTZ, A. P.,CASSEL, M.,KASTENSMIDT, F. L.,COTA, E., AND CARRO, L. 2007. Crosstalk-and seu-aware networks on chips. IEEE Des. Test Comput. 24, 4, 340-350.
53. FRANTZ, A. P., KASTENSMIDT, F. L., CARRO, L., AND COTA, E. 2006b. Evaluation of seu and crosstalk effects in network-on-chip switches. In Proceedings of the Symposium on Integrated Circuits and Systems Design (SBCCI06).
54. FU, B. AND AMPADU, P. 2009. On hamming product codes with type-ii hybrid arq for on-chip interconnects. IEEE Trans. Circ. Syst. I: Regular Papers 56, 9, 2042-2054.
55. FUKUSHIMA, Y., FUKUSHI, M., AND HORIGUCHI, S. 2009. Fault-tolerant routing algorithm for network on chip without virtual channels. In Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT09). 313-321.
56. FURBER, S. 2006. Living with failure: Lessons from nature In Proceedings of the European Test Symposium (ETS06). 4-8.
57. GADLAGE, M., AHLBIN, J.,NARASIMHAM, B., BHUVA, B.,MASSENGILL, L., REED, R., SCHRIMPF, R., AND VIZKELETHY, G. 2010. Scaling trends in set pulse widths in sub-100 nm bulk cmos processes. IEEE Trans. Nuclear Sci. 57, 6, 3336-3341.
58. GANGULY, A., PANDE, P. P., AND BELZER, B. 2009. Crosstalk-aware channel coding schemes for energy efficient and reliable noc interconnects. IEEE Trans. Very Large Scale Inter Syst. 17, 11, 1626-1639.
59. GANGULY, A.,PANDE, P. P.,BELZER, B., AND GRECU, C. 2007. Addressing signal integrity in networks on chip interconnects through crosstalk-aware double error correction coding. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI07). 317-324.
60. GIZOPOULOS, D.,PSARAKIS, M.,ADVE, S. V.,RAMACHANDRAN, P.,HARI, S. K. S.,SORIN, D.,BISWAS, A. M. A., AND VERA, X. 2011. Architectures for online error detection and recovery in multicore processors. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE11).
61. GLASS, C. J. AND NI, L. M. 1993. Fault-tolerant wormhole routing in meshes. In Proceedings of the 23rd International Fault-Tolerant Computing Digest of Papers Symposium (FTCS93). 240-249.
62. GRECU, C., IVANOV, A., PANDE, R., JANTSCH, A., SALMINEN, E.,OGRAS, U., AND MARCULESCU, R. 2007. Towards open network-on-chip benchmarks. In Proceedings of the 1st International Symposium on Networks-on-Chip (NOCS07).
63. GRECU, C., IVANOV, A., SALEH, R., AND PANDE, P. P. 2006a. Noc interconnect yield improvement using crosspoint redundancy. In Proceedings of the 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT06). 457-465.
64. GRECU, C., IVANOV, A.,SALEH, R.,SOGOMONYAN, E., AND PANDE, P. P. 2006b. On-line fault detection and location for noc interconnects. In Proceedings of the 12th IEEE InternationalOn-Line Testing Symposium (IOLTS06). 145-150.
65. HAZUCHA, P.,KARNIK, T.,MAIZ, J.,WALSTRA, S., BLOECHEL, B., TSCHANZ, J.,DERMER, G.,HARELAND, S., ARMSTRONG, P., AND BORKAR, S. 2003. Neutron soft error rate measurements in a 90-nm cmos process and scaling trends in sram from 0.25-mu;m to 90-nm generation. In IEEE International Electron Devices Meeting Technical Digest (IEDM03). 21.5.1-21.5.4.
66. HEGDE, R. AND SHANBHAG, N. 2000. Toward achieving energy efficiency in presence of deep submicron noise. IEEE Trans. Syst. 8, 4, 379-391.
67. HERNANDEZ, C., FEDERICO, F., SANTONJA, V., AND DUATO, J. 2009. A new mechanism to deal with process variability in noc links. In Proceedings of the International Parallel and Distributed Processing Symposium (PDPS09). 1-11.
68. HOSKOTE, Y., VANGAL, S., SINGH, A., BORKAR, N., AND BORKAR, S. 2007. A 5-ghz mesh interconnect for a teraflops processor. IEEE Micro 27, 5, 51-61.
69. HU, J. AND MARCULESCU, R. 2004. Dyad-smart routing for networks-on-chip. In Proceedings of the 41st Design Automation Conference (DAC04). 260-263.
70. HUFFMAN, W. C. AND PLESS, V. 2003. Fundamentals of Error-Correcting Codes. Cambridge University Press.
71. INTEL LABS. 2010. The scc platform overview. Tech. rep. revision 0.7, Intel Corporation. http://www.intel.la/content/dam/www/public/us/en/documents/ technology-briefs/intel-labs-single-chip-platform-overviewpaper. pdf.
72. ITRS. 2009. International technology roadmap for semiconductors. Tech. rep., ITRS Technology Working Group. http://www.itrs.net/Links/2009ITRS/ 2009Chapters 2009Tables/2009 Interconnect.pdf.
73. JANTSCH, A., LAUTER, R., AND VITKOWSKI, A. 2005. Power analysis of link level and end-to-end data protection in networks on chip. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS05). Vol. 2. 1770-1773.
74. JOVANOVIC, S., TANOUGAST, C.,WEBER, S., AND BOBDA, C. 2009. A new deadlock-free fault-tolerant routing algorithm for noc interconnections. In Proceedings of the International Conference on Field Programmable Logic (FPL09). 326-331.
75. KAKOEE, M. R., BERTACCO, V., AND BENINI, L. 2011a. A distributed and topology-agnostic approach for on-line noc testing. In Proceedings of the Network on Chip Symposium.
76. KAKOEE, M. R., BERTACCO, V., AND BENINI, L. 2011b. Relinoc: A reliable network for priority-based on-chip communication. In Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE11).
77. KEANE, J. AND KIM, C. 2011. An odometer for cpus. IEEE Spectrum 48, 5, 26-31.
78. KEANE, J., KIM, T.-H., AND KIM, C. H. 2007. An on-chip nbti sensor for measuring pmos threshold voltage degradation. In Proceedings of the International Symposium on Low Power Electronics and Design.
79. KIM, J.,NICOPOULOS, C., PARK, D.,NARAYANAN, V., YOUSIF, M. S., AND DAS, C. R. 2006. A gracefully degrading and energyefficient modular router architecture for on-chip networks. In Proceedings of the International Symposium on Computer Architecture (ISCA06). 4-15.
80. KIM, J., PARK, D., NICOPOULOS, C., VIJAYKRISHNAN, N., AND DAS, C. 2005. Design and analysis of an noc architecture from performance, reliability and energy perspective. In Proceedings of the Symposium on Architecture for Networking and Communications Systems (ANCS05).
81. KIM, Y. B. AND KIM, Y.-B. 2007. Fault tolerant source routing for network-on-chip. In Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT07). 12-20.
82. KOHLER, A. AND RADETZKI, M. 2009. Fault-tolerant architecture and deflection routing for degradable noc switches. In Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chips (NOCS09). 22-31.
83. KOHLER, A., SCHLEY, G., AND RADETZKI, M. 2010. Fault tolerant network on chip switching with graceful performance degradation. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 20, 6, 883-896.
84. KOIBUCHI, M.,MATSUTANI, H.,AMANO, H., AND PINKSTON, T.M. 2008. A lightweight fault-tolerant mechanism for networkon-chip. In Proceedings of the 2nd ACM/IEEE International Symposium on Networks-on-Chip (NoCS08). 13-22.
85. KOUPAEI, F. K., KHADEMZADEH, A., AND JANIDARMIAN, M. 2011. Fault-tolerant application-specific network-onchip. In Proceedings of the World Congress on Engineering and Computer Science.
86. KUHN, K., KENYON, C., KORNFELD, A., LIU, M.,MAHESHWARI, A., KAI SHIH, W., SIVAKUMAR, S., TAYLOR, G., VANDERVOORN, P., AND ZAWADZKI, K. 2008. Managing process variation in Intels 45nm CMOS Technology. Intel Technol. J. 12, 2.
87. LEE, H., CHANG, N., OGRAS, U., AND MARCULESCU, R. 2007. On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus, and network-on-chip approaches. ACMTrans. Des. Autom. Electron. Syst. 12, 3.
88. LEHTONEN, T., LILJEBERG, P., AND PLOSILA, J. 2007a. Analysis of forward error correction methods for nanoscale networks-onchip. In Proceedings of the 2nd International Conference on Nano-Networks (Nano-Net07). Institute for Computer Sciences, Social-Informatics and Telecommunications Engineering, 1-5.
89. LEHTONEN, T., LILJEBERG, P., AND PLOSILA, J. 2007b. Online reconfigurable self-timed links for fault tolerant noc. VLSI Des. 2007, 13.
90. LEHTONEN, T.,WOLPERT, D., LILJEBERG, P., PLOSILA, J., AND AMPADU, P. 2010. Self-adaptive system for addressing permanent errors in on-chip interconnects. IEEE Trans. VLSI Syst. 18, 4, 527-540.
91. LIN, S.-Y., SHEN, W.-C., HSU, C.-C., CHAO, C.-H., AND WU, A.-Y. 2009. Fault-tolerant router with built-in selftest/self-diagnosis and fault-isolation circuits for 2d-mesh based chip multiprocessor systems. In Proceedings of the International Symposium on VLSI Design, Automation and Test (VLSI-DAT09). 72-75.
92. LYSNE, O., PINKSTON, T., AND DUATO, J. 2005. Part ii: A methodology for developing deadlock-free dynamic network reconfiguration processes. IEEE Trans. Parallel Distrib. Syst. 16, 5, 428-443.
93. MAJER, M., BOBDA, C., AHMADINIA, A., AND TEICH, J. 2005. Packet routing in dynamically changing networks on chip. In Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium. 154b-154b.
94. MALKIN, G. AND STEENSTRUP, M. 1995. Distance-vector routing. In Routing in Communication Networks, M. Steenstrup, Ed., Prentice Hall, 83-98.
95. MARCULESCU, R., OGRAS, U., PEH, L.-S., JERGER, N., AND HOSKOTE, Y. 2009. Outstanding research problems in noc design: System, microarchitecture, and circuit perspectives. IEEE Trans. Comput. 28, 1, 3-21.
96. MCPHERSON, J. 2006. Reliability challenges for 45nm and beyond. In Proceedings of the 43rd ACM/IEEE Design Automation Conference (DAC06). 176-181.
97. MEDIRATTA, S. D. AND DRAPER, J. 2007. Performance evaluation of probe-send fault-tolerant network-on-chip router. In Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP07). 69-75.
98. MEJIA, A., FLICH, J., DUATO, J., REINEMO, S.-A., AND SKEIE, T. 2006. Segment-based routing: An efficient faulttolerant routing algorithm for meshes and tori. In Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS06).
99. MEJIA, A., PALESI, M., FLICH, J., KUMAR, S., LOPEZ, P.,HOLSMARK, R., AND DUATO, J. 2009. Region-based routing: A mechanism to support efficient routing algorithms in nocs. IEEE Trans. Syst. 17, 3, 356-369.
100. MINTARNO, E., SKAF, J., ZHENG, R.,VELAMALA, J. B.,CAO, Y.,BOYD, S.,DUTTON, R. W., ANDMITRA, S. 2011. Selftuning for maximized lifetime energy-efficiency in the presence of circuit aging. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 30, 5, 760-773.
101. MIRANDA, E. AND SUNE, J. 2004. Electron transport through broken down ultra-thin sio2 layers in mos devices. Microelectron. Reliabil. 44, 1, 1-23.
102. MITRA, S., ZHANG, M., WAQAS, S., SEIFERT, N., GILL, B., AND KIM, K. S. 2006. Combinational logic soft error correction. In Proceedings of the IEEE International Test Conference (ITC06). 1-9.
103. MOY, J. 1995. Link-state routing. In Routing in Communication Networks, M. Ste, Ed., Prentice Hall, 135-157.
104. MURALI, S., ATIENZA, D., BENINI, L., AND DE MICHELI, G. 2006. A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip. In Proceedings of the 43rd ACM/IEEE Design Automation Conference (DAC06). 845-848.
105. MURALI, S., THEOCHARIDES, T.,VIJAYKRISHNAN, N., IRWIN, M.,BENINI, L., AND DEMICHELI, G. 2005. Analysis of error recovery schemes for networks on chips. IEEE Des. Test Comput. 22, 5, 434-442.
106. NICOLAIDIS, M. 1999. Time redundancy based soft-error tolerance to rescue nanometer technologies. In Proceedings of the 17th IEEE VLSI Test Symposium. 86-94.
107. OGRAS, U., HU, J., AND MARCULESCU, R. 2005. Key research problems in noc design: A holistic perspective. In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS05).
108. OWENS, J., DALLY, W., HO, R., JAYASIMHA, D., KECKLER, S., AND PEH, L.-S. 2007. Research challenges for on-chip interconnection networks. IEEE Micro 27, 5, 96-108.
109. PALESI, M., KUMAR, S., AND CATANIA, V. 2010. Leveraging partially faulty links usage for enhancing yield and performance in networks-on-chip. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 29, 426-440.
110. PANDE, P. P.,GANGULY, A.,FEERO, B.,BELZER, B., AND GRECU, C. 2006. Design of low power and reliable networks on chip through joint crosstalk avoidance and forward error correction coding. In Proceedings of the 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT06). 466-476.
111. PARIKH, R. AND BERTACCO, V. 2011. Formally enhanced runtime verification to ensure noc functional correctness. In Proceedings of the 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO11). 410-419.
112. PARK, D.,NICOPOULOS, C.,KIM, J., VIJAYKRISHNAN, N., AND DAS, C. R. 2006. Exploring fault-tolerant network-onchip architectures. In Proceedings of the International Conference on Dependable Systems and Networks (DSN06). IEEE Computer Society, Los Alamitos, CA, 93-104.
113. PATOOGHY, A. AND MIREMADI, S. G. 2008. Ltr: A low-overhead and reliable routing algorithm for network on chips. In Proceedings of the International SoC Design Conference (ISOCC08). Vol. 1.
114. PATOOGHY, A.,MIREMADI, S. G., AND SHAFAEI, M. 2010. Crosstalk modeling to predict channel elay in networkon-chips. In Proceedings of the IEEE International Conference on Computer Design (ICCD10). 396-401.
115. PIRRETTI, M., LINK, G. M., BROOKS, R. R., VIJAYKRISHNAN, N., KANDEMIR, M. T., AND IRWIN, M. J. 2004. Fault tolerant algorithms for network-on-chip interconnect. In Proceedings of the International Symposium on VLSI (ISVLSI04). IEEE Computer Society, Los Alamitos, CA, 46-51.
116. PUENTE, V.,GREGORIO, J. A.,VALLEJO, F., AND BEIVIDE, R. 2008. Immunet: Dependable routing for interconnection networks with arbitrary topology. IEEE Trans. Comput. 57, 12, 1676-1689.
117. RADETZKI, M. 2011. Fault-tolerant differential q routing in arbitrary noc topologies. In Proceedings of the International Conference on Embedded and Ubiquitous Computing (EUC11). 33-40.
118. RAIK, J., UBAR, R., AND GOVIND, V. 2007. Test configurations for diagnosing faulty links in noc switches. In Proceedings of the 12th IEEE European Test Symposium (ETS07). 29-34.
119. RANTALA, V., LEHTONEN, T., LILJEBERG, P., AND PLOSILA, J. 2009. Multi network interface architectures for fault tolerant network-on-chip. In Proceedings of the International Symposium on Signals, Circuits and Systems. 1-4.
120. RAVINDRAN, D. K. 2009. Structural fault-tolerance on the noc circuit level. Tech. rep., Institut fur Technische Informatik, Universitat Stuttgart. June.
121. RODRIGO, S., FLICH, J., DUATO, J., AND HUMMEL, M. 2008. Efficient unicast and multicast support for cmps. In Proceedings of the 41st IEEE/ACM International Symposium on Microarchitecture (MICRO08). 364-375.
122. RODRIGO, S., FLICH, J., ROCA, A., MEDARDONI, S., BERTOZZI, D., CAMACHO, J., SILLA, F., AND DUATO, J. 2010. Addressing manufacturing challenges with cost-efficient fault tolerant routing. In Proceedings of the 4th ACM/IEEE International Networks-on-Chip Symposium (NOCS10). 25-32.
123. ROSSI, D., ANGELINI, P., AND METRA, C. 2007. Configurable error control scheme for noc signal integrity. In Proceedings of the International On-Line Testing Symposium (IOLTS07). 43-48.
124. SAHA, S. 2010. Modeling process variability in scaled cmos Technology. IEEE Des. Test Comput. 27, 2, 8-16.
125. SANYO SEMICONDUCTORS. 2011. Quality and reliability handbook ver 3. http://semicon.sanyo.com/en/reliability/.
126. SCHROEDER, M. D.,BIRRELL, A. D.,BURROWS, M.,MURRAY, H.,NEEDHAM, R. M.,RODEHEFFER, T. L., SATTERTHWAITE, E. H., AND THACKER, C. P. 1991. Autonet: A high-speed, self-configuring local area network using pointto-point links. IEEE J. Selected Areas Comm. 9, 8, 1318-1335.
127. SCHAFER,M.,HOLLSTEIN, T.,ZIMMER,H., ANDGLESNER,M. 2005. Deadlock-free routing and component placement for irregular mesh-based networks-on-chip. In Proceedings of the International Conference on Computer Aided Design (ICCAD05). 238-245.
128. SCHONWALD, T., ZIMMERMANN, J., BRINGMANN, O., AND ROSENSTIEL, W. 2007. Fully adaptive fault-tolerant routing algorithm for network-on-chip architectures. In Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD07). 527-534.
129. SHAMSHIRI, S., GHOFRANI, A., AND CHENG, K.-T. 2011. End-to-end error correction and online diagnosis for on-chip networks. In Proceedings of the International Test Conference.
130. SHIVAKUMAR, P.,KISTLER, M.,KECKLER, S. W., BURGER, D., AND ALVISI, L. 2002. Modeling the effect of technology trends on the soft error rate of combinational logic. In Proceedings of the International Conference on Dependable Systems and Networks.
131. SHOOMAN, M. L. 2002. Reliability of Computer Systems and Networks: Fault Tolerance, Analysis, and Design. John Wiley & Sons.
132. SONG, W., EDWARDS, D., NUNEZ-YANEZ, J., AND DASGUPTA, S. 2009. Adaptive stochastic routing in fault-tolerant on-chip networks. In Proceedings of the 3rd ACM/IEEE International Symposium on Networks-on-Chip (NoCS09). 32-37.
133. SRIDHARA, S. AND SHANBHAG, N. 2005. Coding for system-on-chip networks: A unified framework. IEEE Trans. VLSI Syst. 13, 6, 655-667.
134. STRANO, A., BERTOZZI, D., TRIVINO, F., SANCHEZ, J. L., ALFARO, F. J., AND FLICH, J. 2012. Osr-lite: Fast and deadlock-free noc reconfiguration framework. In Proceedings of the International Conference on Embedded Computer Systems: Architectures, Modelling and Simulation.
135. TAKEDA, E. AND YANG, C. 1995. Hot-Carrier Effects in MOS Devices. Academic Press.
136. TAMHANKAR, R.,MURALI, S., AND DE MICHELI, G. 2005. Performance driven reliable link design for networks on chips. In Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC05). Vol. 2. 749-754.
137. VANGAL, S., HOWARD, J., RUHL, G., DIGHE, S., WILSON, H., TSCHANZ, J., FINAN, D., IYER, P., SINGH, A., JACOB, T., JAIN, S., VENKATARAMAN, S., HOSKOTE, Y., AND BORKAR, N. 2007. An 80-tile 1.28tflops network-on-chip in 65nm cmos. In Digest of Technical Papers of the IEEE International Solid-State Circuits Conference (ISSCC07). 98-589.
138. VITERBI, A. J. 1971. Convolutional codes and their performance in communication systems. IEEE Trans. Comm. Technol. 19, 5, 751-772.
139. VITKOVSKI, A., JANTSCH, A., LAUTER, R., HAUKILAHTI, R., AND NILSSON, E. 2008. Low-power and error protection coding for network-on-chip traffic. IET Comput. Digital Techn. 2, 6, 483-492.
140. VITKOVSKIY, A., SOTERIOU, V., AND NICOPOULOS, C. 2010. A fine-grained link-level fault-tolerant mechanism for networks-onchip. In Proceedings of the IEEE International Computer Design Conference (ICCD10). 447-454.
141. WALKER, M. 2000. Modeling the wiring of deep submicron ics. IEEE Spectrum 37, 3, 65-71.
142. WITTMANN, R., PUCHNER, H.,HINH, L., CERIC, H., GEHRING, A., AND SELBERHERR, S. 2005. Simulation of dynamic nbti degradation for a 90nm cmos Technology. In Proceedings of the Nanotechnology Conference.
143. WU, E., LAI, W., NOWAK, E., MCKENNA, J., VAYSHENKER, A., AND HARMON, D. 2001. Interplay of voltage and temperature acceleration of oxide breakdown for ultra-thin oxides. Microelectron. Engin. 59, 25-31.
144. WU, J. ANDWANG, D. 2002. Fault-tolerant and deadlock-free routing in 2-d meshes using rectilinear-monotone polygonal fault blocks. In Proceedings of the International Conference on Parallel Processing. 247-254.
145. XINMING, D. AND XUEMEI, S. 2010. Fault-tolerant routing in a prdt(2,1)-based noc. In Proceedings of the 2nd International Computer Engineering and Technology Conference (ICCET10).
146. YAGHINI, P. M., EGHBAL, A., PEDRAM, H., AND ZARANDI, H. R. 2011. Investigation of transient fault effects in synchronous and asynchronous network on chip router. J. Syst. Archit. 57, 1, 61-68.
147. YANG, Y. 2010. Issues of esd protection in nano-scale cmso. Ph.D. thesis, George Mason University, Fairfax, Virginia, USA.
148. YU, A. J. AND LEMIEUX, G. G. 2005. Fpga defect tolerance: Impact of granularity. In Proceedings of the IEEE International Conference on Field-Programmable Technology (FPT05). 189-196.
149. YU, Q. AND AMPADU, P. 2008. Adaptive error control for noc switch-to-switch links in a variable noise environment. In Proceedings of the IEEE International Symposium on Defect and Fault Tolerance of VLSI Systems (DFTVS08). 352-360.
150. YU, Q. AND AMPADU, P. 2010. Transient and permanent error co-management method for reliable networkson-chip. In Proceedings of the 4th ACM/IEEE International Networks-on-Chip Symposium (NOCS10). 145-154.
151. YU, Q. AND AMPADU, P. 2011. A dual-layer method for transient and permanent error co-management in noc links. IEEE Trans. Circ. Syst. II: Express Briefs 58, 1, 36-40.
152. YU, Q. AND AMPADU, P. 2012. Dual-layer adaptive error control for network-on-chip links. IEEE Trans. VLSI. Syst. 20, 7, 1304-1317.
153. YU, Q., CANO, J., FLICH, J., AND AMPADU, P. 2012. Transient and permanent error control for high-end multiprocessor systems-on-chip. In Proceedings of the 6th IEEE/ACM International Symposium on Networks on Chip (NoCS12). 169-176.
154. YU, Q., ZHANG, B., LI, Y., AND AMPADU, P. 2010. Error control integration scheme for reliable noc. In Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS10). 3893-3896.
155. YU, Q., ZHANG, M., AND AMPADU, P. 2011. Exploiting inherent information redundancy to manage transient errors in noc routing arbitration. In Proceedings of the IEEE Network on Chip Symposium (NoCS11).
156. ZHANG B. AND ORSHANSKY, M. 2008. Modeling of nbti-induced pmos degradation under arbitrary dynamic temperature variation. In Proceedings of the 9th International Symposium on Quality Electronic Design (ISQED08). 774-779.
157. ZHANG, M. AND SHANBHAG, N. 2006. Soft-error-rate-analysis (sera) methodology. IEEE Trans. Comput.-Aid. Des. Integr. Circ. Syst. 25, 10, 2140-2155.
158. ZHANG, Y. AND JIANG, J. 2008. Bibliographical review on reconfigurable fault-tolerant control systems. Ann. Rev. Control 32, 229-252.
159. ZHANG, Y., LI, H., AND LI, X. 2009. Selected crosstalk avoidance code for reliable network-on-chip. J. Comput. Sci. Technol. 24, 6, 1074-1085.
160. ZHANG, Y., PARIKH, D., SANKARANARAYANAN, K., SKADRON, K., AND STAN, M. 2003. Hotleakage: A temperatureaware model of subthreshold and gate leakage for architects. Tech. rep. CS-2003-05, University of Virgiania, Department of Computer Science.
161. March. ZHANG, Z., GREINER, A., AND TAKTAK, S. 2008. A reconfigurable routing algorithm for a fault-tolerant 2d-mesh network-on-chip. In Proceedings of the Design Automation Conference (DAC08). 441-446.
162. ZIMMER, H. AND JANTSCH, A. 2003. A fault model notation and error-control scheme for switch-to-switch buses in a network-onchip. In Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis. 188-193.