Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration

NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip

Volumn , Issue , 2011, Pages 105-112

  Yu, Qiaoyan ^a   Zhang, Meilin ^a   Ampadu, Paul ^a  

^a University of Rochester   (United States)

Author keywords

arbiter; fault tolerant; information redundancy; Networks on Chip; on chip interconnect; reliability; transient error; triple modular redundancy

Indexed keywords

ARBITER; FAULT TOLERANT; INFORMATION REDUNDANCIES; NETWORKS ON CHIPS; ON CHIP INTERCONNECT; TRANSIENT ERROR; TRIPLE-MODULAR REDUNDANCY;

ASYNCHRONOUS SEQUENTIAL LOGIC; ERRORS; NETWORK ARCHITECTURE; REDUNDANCY;

ROUTERS;

EID: 79960315249     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1999946.1999964     Document Type: Conference Paper

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