Structural test for graceful degradation of NoC switches

Proceedings - 16th IEEE European Test Symposium, ETS 2011

Volumn , Issue , 2011, Pages 183-188

  Dalirsani, Atefe ^a   Holst, Stefan ^a   Elm, Melanie ^a   Wunderlic, Hans Joachim ^a  

^a UNIVERSITY OF STUTTGART   (Germany)

Author keywords

Graceful degradation; Logic Diagnosis; Network on Chip; Performability

Indexed keywords

AREA OVERHEAD; DIAGNOSIS METHODS; FAULT-TOLERANT; FUNCTIONAL BEHAVIORS; GRACEFUL DEGRADATION; INHERENT REDUNDANCY; LOGIC DIAGNOSIS; NETWORK ON CHIP; NETWORKS ON CHIPS; NOC SWITCH; PERFORMABILITY; SIDE EFFECT; STRUCTURAL TESTING; STRUCTURAL TESTS; SWITCH DESIGNS; SWITCH FUNCTION; SWITCH PORTS;

ASYNCHRONOUS SEQUENTIAL LOGIC; DEFECTS; DEGRADATION; VLSI CIRCUITS;

TIME SWITCHES;

EID: 80052013368     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ETS.2011.33     Document Type: Conference Paper

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