Design and analysis of an NoC architecture from performance, reliability and energy perspective

2005 Symposium on Architectures for Networking and Communications Systems, ANCS 2005

Volumn , Issue , 2005, Pages 173-182

  Kim, Jongman ^a   Park, Dongkook ^a   Nicopoulos, Chrysostomos ^a   Vijaykrishnan, N ^a   Das, C R ^a  

^a The Pennsylvania State University   (United States)

Author keywords

Adaptive routing; Networks On chip; Reliability

Indexed keywords

ADAPTIVE ROUTING; ANALYTICAL MODEL; COMPLETE SOLUTIONS; CRITICAL ISSUES; CYCLE-ACCURATE SIMULATORS; DEEP SUB-MICRON TECHNOLOGY; DESIGN AND ANALYSIS; ENERGY CONSUMPTION; ENERGY PERSPECTIVES; ERROR DETECTION AND CORRECTION; ERROR PROTECTION; FAST METHODS; HARDWARE COMPONENTS; LOW-LATENCY; NETWORK-ON-CHIP ARCHITECTURES; NETWORKS-ON-CHIP; NOC ARCHITECTURES; ON-CHIP NETWORKS; PACKET-BASED COMMUNICATION; PERFORMANCE TRADE-OFF; POWER OVERHEAD; ROUTER ARCHITECTURE; SYSTEM ON CHIP DESIGN; TRANSIENT FAULTS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; ELECTRIC NETWORK TOPOLOGY; EMBEDDED SYSTEMS; ENERGY EFFICIENCY; ERROR CORRECTION; ERROR DETECTION; FAULT TOLERANCE; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; PROGRAMMABLE LOGIC CONTROLLERS; RELIABILITY ANALYSIS; ROUTERS; WIRELESS SENSOR NETWORKS;

QUALITY ASSURANCE;

EID: 67650538109     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ANCS.2005.4675277     Document Type: Conference Paper

References (36)

1. A. Adriahantenaina, H. Charlery, A. Greiner, L. Moriiez, and C. A. Zeferino. SPIN: A Scalable, Packet Switched, On-chip Micro-network. In Proceedings of the DATE, 2003.
2. A. Agarwal. Limits on interconnection network. IEEE Transaction on Parallel and Distibuted Systems, 2(4), 1991.
3. L. Anghel and M. Nicolaidis. Cost Reduction and Evaluation of Temporary Faults Detecting Technique. In DATE 2000, pages 591-598, March 2000.
4. J. M. Baker, S. B. Jr.,M. Bucciero, B. Gold, and R.Mahajan. SCMP:A Single-Chip Message Passing Parallel Computer. In Parallel and Distributed Processing Techniques and Applications (PDPTA'02), pages 1485-1491, 2002.
5. L. Benini and G. D. Micheli. Networks on Chips: A New SoC Paradigm. IEEE Computer, 35(1):70-78, 2002. (Pubitemid 34069383)
6. D. Bertozzi, L. Benini, and G. D. Micheli. Low Power Error Resilient Encoding for On-chip Data Buses. In Proceedings of Design Automation and Test Conference in Europe, March 2002.
7. D. Bertozzi, L. Benini, and G. D. Micheli. Low power error resilient encoding for on-chip data buses. In Proceedings of 2002 DATE, 2002.
8. Y. Cao, C. Hu, A. B. Kahng, S. Muddu, D. Stroobandt, and D. Sylvester. Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Designs. In International Conference on Computer-Aided Design, pages 56-61, 2000. (Pubitemid 32188480)
9. W. J. Dally and B. Towles. Route Packets, Not Wires: On-Chip Interconnection Networks. In Proceedings of the 38th DAC, June 2001.
10. W. J. Dally and B. Towles. Principles and Practices of Interconnection Networks. Morgan Kaufmann, 2003.
11. T. Dumitras, S. Kerner, and R. Marculescu. Towards On-chip Fault-Tolerant Communication. In Proc. Asia & South Pacific Design Automation Conf.(ASP-DAC), January 2003.
12. N. Eisley and L.-S. Peh. High-level power analysis for on-chip networks. In Proceedings of the 7th International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES), September 2004.
13. A. H. et al. Network on a Chip: An Architecture for Billion Transistor Era. In Proc. of the IEEE NorChip Conference, November 2000.
14. D. Flynn. AMBA: Enabling Reusable On-Chip Design. In IEEE Micro, pages 20-27, July 1997. (Pubitemid 127559769)
15. R. Ho, K. W. Mai, andM. A. Horowitz. The Future of Wires. In Proceedings of the IEEE, pages 490-504, 2001. (Pubitemid 33766588)
16. J. Hu and R. Marculescu. Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures. In Proc. Design, Automation and Test in Europe Conference, 2003.
17. J. Huh, S. W. Keckler, and D. Burger. Exploring the Design Space of Future CMPs. In Proceedings of the International Conference on Parallel Architectures and Compilation Techniques (PACT), 2001.
18. R. M. Jingcao Hu. Energy-aware mapping for tile-based noc architectures under performance constraints. In Proc. of ASPDAC, January 2003.
19. E. Jung, K. K. H. Yum, and C. R. Das. Calculation of deadline missing probability in a qos capable cluster interconnect. In NCA '01: Proceedings of the IEEE International Symposium on Network Computing and Applications (NCA'01), page 36, Washington, DC, USA, 2001. IEEE Computer Society.
20. J. Kim, D. Park, T. Theocharides, N. Vijaykrishnan, and C. R. Das. A low latency router supporting adaptivity for on-chip router. In 42nd DAC, June 2005.
21. A. Krstic, Y. M. Jiang, and K. T. Cheng. Pattern Generation for Delay Testing and Dynamic Timing Analysis Considering Power-Supply Noise Effects. IEEE Transactions on CAD, 20(3):416-425, March 2001. (Pubitemid 32407239)
22. S. Kumar, A. Jantsch, J. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja, and A. Hemani. A Network on Chip Architecture and Design Methodology. In Proc. IEEE Computer Society Annual Symposium on VLSI, pages 105-112, 2002.
23. J. Liang, S. Swaminathan, and R. Tessier. aSOC: A Scalable, Single-Chip Communications Architecture. In the IEEE International Conference on Parallel Architectures and Compilation Techniques, pages 524-529, October
24. R. Marculescu. Networks-On-Chip: The Quest for On-Chip Fault-Tolerant Communication. In Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI'03), 2003.
25. C. A. Moritz, D. Yeung, and A. Agarwal. SimpleFit: A Framework for Analyzing Design Trade-Offs in Raw Architectures. IEEE TPDS, 12(7):730-742, 2001.
26. V. Raghunathan, M. B. Srivastava, and R. K. Gupta. Energy-Aware System Design: A Survey of Techniques for Energy Efficient On-Chip Communication. In Proceedings of the 40th DAC, pages 900-905, 2003.
27. H. Sarbazi-Azad, M. Ould-Khaoua, and L. M. Mackenzie. A performance model of adaptive wormhole routing in k-ary n-cubes in the presence of digit-reversal traffic. J. Supercomput., 22(2):139-159, 2002. (Pubitemid 34474937)
28. L. Shang, L.-S. Peh, and N. K. Jha. Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. In Proc. HPCA, February 2003.
29. K. L. Shepard and V. Narayanan. Noise in Deep Submicron Digital Design. In IEEE/ACM ICCAD-96, pages 524-531, November 1996.
30. P. Shivakumar, M. Kistler, S. Keckler, D. Burger, and L. Alvisi. Modeling the Effect of Technology Trends on the Soft Error Rate of Combinational Logic. InProceedings of the International Conference on Dependable Systems and Networks, 2002.
31. Sonics, Incorporated. http://www.sonicsinc.com.
32. S. R. Sridhara and N. R. Shanbhag. Coding for system-on-chip networks: a unified framework. In DAC, pages 103-106, June 2004.
33. P. Vellanki, N. Banerjee, and K. Chatha. Quality-of-Service and Error Control Techniques for Network-on-Chip Architectures. In Proceedings of the Great Lakes Symposium on VLSI, 2004.
34. T. T. Ye, L. Benini, and G. D. Micheli. Packetized On-Chip Interconnect Communication Analysis for MPSoC. In Proc. Design Automation and Test in Europe, pages 344-349, 2003.
35. H. Zhang, M. Wan, V. George, and J. Rabaey. Interconnect Architecture Exploration for Low-Energy Reconfigurable Single-Chip DSPs. In Proceedings of the WVLSI, April 1999.
36. H. Zimmer and A. Jantsch. A Fault Model Notation and Error-Control Scheme for Switch-to-Switch Buses in a Network-on-Chip. In Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign & system synthesis, pages 188-193, 2003.