Routing table minimization for irregular mesh NoCs

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2007, Pages 942-947

  Bolotin, Evgeny ^a   Cidon, Israel ^a   Ginosar, Ran ^a   Kolodny, Avinoam ^a  

^a TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; COMPUTER SIMULATION; DECISION THEORY; ELECTRIC POWER UTILIZATION; NETWORK ROUTING; OPTIMIZATION;

MESH NETWORKS; NETWORK ON CHIP (NOC); ROUTING TABLE MINIMIZATION; STATIC ROUTING;

MICROPROCESSOR CHIPS;

EID: 34250888675     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2007.364414     Document Type: Conference Paper

References (24)

1. ITRS, 2003 edition, Design Chapter.
2. J. Liu et al., "Interconnect intellectual property for Network-on-Chip (NoC)," JSA, Feb. 2004
3. Z. Guz et al., "Efficient Link Capacity and QoS Design for Wormhole Network-on-Chip", DATE 2006
4. E. Bolotin, et al, "QNoC: QoS Architecture and Design Process for Networks on Chip", JSA, Feb 2004
5. K. Goossens et al. "A design flow for application-specific networks on chip with guaranteed performance to accelerate SOC design and verification. DATE, 2005.
6. F.Moraes et al,"HERMES; an Infrastructure for Low Area Overhead Packet-switching NoC," VLSI Journal, 2004.
7. M. Dall'Osso et al, "XPIPES: a Latency Insensitive Parameterized Network-on-Chip Architecture" ICCD, 2003.
8. M. Millberg et al., "The Nostrum Backbone-A Communication Protocol Stack for Networks on Chip," VLSI Design Conf., Jan 2004.
9. D.S. Tortosa and J. Nurmi, "Proteo: A New Approach to Network-on-Chip," IASTED CSN'02, Spain, 2002.
10. M. Majer et al., "Packet Routing in Dynamically Changing Networks on Chip", IPDPS 2005.
11. S. Kumar et al., "A Network on Chip Architecture and Design Methodology," ISVLSI 2002.
12. Banerjee N. et al. "A power and performance model for network-on-chip architectures", DATE 2004.
13. J. Hu, R. Marculescu, "DyAD - Smart Routing for Networks-on-Chip, " DAC 2004.
14. J.Henkel, W.Wolf, and S.Chakradhar, "On Chip Networks: A scalable communication-centric embedded system design paradigm", in Procedings, VLSI Design 2004
15. D. Bertozzi et al., "NoC synthesis flow for customized domain specific multiprocessor systems-on-chip". IEEE Trans. on Parallel and Dist.Systems, 16(2):113-129, 2005.
16. A. Hemani et al., Network on a chip: An architecture for billion transistor era. In IEEE NorChip, 2000.
17. W. Dally et al, "Deadlock-free message routing in multiprocessor interconnection networks," IEEE Trans. Comp., C-36(5):547-553, 1987.
18. J. Van Leeuwen and R.B. Tan, "Interval routing," The Computer Journal, 30(4):298-307, Aug. 1987.
19. M.E. Gómez et al., "A Memory-Effective Routing Strategy for Regular Interconnection Networks," IPDPS 2005.
20. S. Borkar et al., "iWarp: An Integrated Solution to High-Speed Parallel Computing," Proc. Supercomputing, 1988
21. E. Bolotin, at al., "Efficient Routing in Irregular Topology NoCs", CCIT Report #554, EE Dept, Technion, Sep. 2005
22. K. Srinivasan, at al. "An Automated Technique for Topology and Route Generation of Application Specific On-Chip Interconnection Networks", ICCAD 2005
23. M. Schafer, et al. "Deadlock-free routing and component placement for irregular mesh-based networks-on-chip,"ICCAD 2005.
24. M.Palesi, S.Kumar, R.Holsmark. A Method for Router Table Compression for Application Specific Routing in Mesh Topology NoC Architectures", SAMOS VI Workshop, 2006.