메뉴 건너뛰기




Volumn 28, Issue 1, 2009, Pages 3-21

Outstanding research problems in NoC design: System, microarchitecture, and circuit perspectives

Author keywords

Energy and power consumption; Multiprocessor systems on chip (MPSoCs); Networks on chip (NoCs); On chip communication

Indexed keywords

COMMUNICATION INFRASTRUCTURE; COMMUNICATION PARADIGM; COMMUNICATION PROBLEMS; GENERAL DESCRIPTION; GLOBAL INTERCONNECTS; MICRO ARCHITECTURES; MULTIPROCESSOR SYSTEMS ON CHIPS; NETWORK-ON-CHIP ARCHITECTURES; NETWORKS ON CHIPS; NOC ARCHITECTURES; NOC DESIGN; ON CHIP COMMUNICATION; ON CHIPS; POWER CONSUMPTION; PROBLEM DESCRIPTION; RESEARCH PROBLEMS;

EID: 66549114708     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2008.2010691     Document Type: Article
Times cited : (624)

References (181)
  • 2
    • 84893818178 scopus 로고    scopus 로고
    • Micro-network for SoC: Implementation of a 32-port SPIN network
    • Mar.
    • A. Adriahantenaina and A. Greiner, "Micro-network for SoC: Implementation of a 32-port SPIN network," in Proc. Des., Autom. Test Eur. Conf., Mar. 2003, pp. 1128-1129.
    • (2003) Proc. Des., Autom. Test Eur. Conf. , pp. 1128-1129
    • Adriahantenaina, A.1    Greiner, A.2
  • 4
    • 33847092866 scopus 로고    scopus 로고
    • A scalable test strategy for network-on-chip routers
    • Nov.
    • A. M. Amory et al., "A scalable test strategy for network-on-chip routers," in Proc. IEEE Int. Test Conf., Nov. 2005, pp. 591-599.
    • (2005) Proc. IEEE Int. Test Conf. , pp. 591-599
    • Amory, A.M.1
  • 8
    • 77957933800 scopus 로고    scopus 로고
    • Delay insensitive system-on-chip interconnect using 1-of-4 data encoding
    • Mar.
    • W. Bainbridge and S. Furber, "Delay insensitive system-on-chip interconnect using 1-of-4 data encoding," in Proc. Int. Symp. Asynchronous Circuits Syst., Mar. 2001, pp. 118-126.
    • (2001) Proc. Int. Symp. Asynchronous Circuits Syst. , pp. 118-126
    • Bainbridge, W.1    Furber, S.2
  • 9
    • 34547471544 scopus 로고    scopus 로고
    • Design tradeoffs for tiled CMP on-chip networks
    • Jun.
    • J. Balfour and W. J. Dally, "Design tradeoffs for tiled CMP on-chip networks," in Proc. Int. Conf. Supercomputing, Jun. 2006, pp. 187-198.
    • (2006) Proc. Int. Conf. Supercomputing , pp. 187-198
    • Balfour, J.1    Dally, W.J.2
  • 10
    • 3042565282 scopus 로고    scopus 로고
    • A power and performance model for network-on-chip architectures
    • Feb.
    • N. Banerjee, P. Vellank, and K. S. Chatha, "A power and performance model for network-on-chip architectures," in Proc. Des., Autom. Test Eur. Conf., Feb. 2004, pp. 1250-1255.
    • (2004) Proc. Des., Autom. Test Eur. Conf. , pp. 1250-1255
    • Banerjee, N.1    Vellank, P.2    Chatha, K.S.3
  • 11
    • 78650050851 scopus 로고    scopus 로고
    • Highly scalable network on chip for reconfigurable systems
    • Nov.
    • T. A. Bartic et al., "Highly scalable network on chip for reconfigurable systems," in Proc. Int. Symp. Syst.-on-Chip, Nov. 2003, pp. 79-82.
    • (2003) Proc. Int. Symp. Syst.-on-chip , pp. 79-82
    • Bartic, T.A.1
  • 12
    • 61349149487 scopus 로고    scopus 로고
    • Low power and energy efficient asynchronous design
    • Dec.
    • P. Beerel and M. E. Roncken, "Low power and energy efficient asynchronous design," J. Low Power Electron., vol. 3, no. 3, pp. 234-253, Dec. 2007.
    • (2007) J. Low Power Electron. , vol.3 , Issue.3 , pp. 234-253
    • Beerel, P.1    Roncken, M.E.2
  • 14
    • 44149123610 scopus 로고    scopus 로고
    • Dynamic voltage and frequency scaling architecture for units integration within a GALS NoC
    • E. Beigne, F. Clermidy, S. Miermont, and P. Vivet, "Dynamic voltage and frequency scaling architecture for units integration within a GALS NoC," in Proc. Int. Symp. Netw. Chip, 2008, pp. 129-138.
    • (2008) Proc. Int. Symp. Netw. Chip , pp. 129-138
    • Beigne, E.1    Clermidy, F.2    Miermont, S.3    Vivet, P.4
  • 15
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: A new SoC paradigm
    • Jan.
    • L. Benini and G. De Micheli, "Networks on chips: A new SoC paradigm," Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002.
    • (2002) Computer , vol.35 , Issue.1 , pp. 70-78
    • Benini, L.1    De Micheli, G.2
  • 16
    • 14844365666 scopus 로고    scopus 로고
    • NoC synthesis flow for customized domain specific multiprocessor systems-on-chip
    • Feb.
    • D. Bertozzi et al., "NoC synthesis flow for customized domain specific multiprocessor systems-on-chip," IEEE Trans. Parallel Distrib. Syst., vol. 16, no. 2, pp. 113-129, Feb. 2005.
    • (2005) IEEE Trans. Parallel Distrib. Syst. , vol.16 , Issue.2 , pp. 113-129
    • Bertozzi, D.1
  • 17
    • 20444467586 scopus 로고    scopus 로고
    • Error control schemes for on-chip communication links: The energy-reliability tradeoff
    • Jun.
    • D. Bertozzi, L. Benini, and G. De Micheli, "Error control schemes for on-chip communication links: The energy-reliability tradeoff," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 6, pp. 818-831, Jun. 2005.
    • (2005) IEEE Trans. Comput.-aided Design Integr. Circuits Syst. , vol.24 , Issue.6 , pp. 818-831
    • Bertozzi, D.1    Benini, L.2    De Micheli, G.3
  • 20
    • 27344444925 scopus 로고    scopus 로고
    • A router architecture for connection-oriented service guarantees in the MANGO clockless network-on-chip
    • DOI 10.1109/DATE.2005.36, 1395761, Proceedings - Design, Automation and Test in Europe, DATE '05
    • T. Bjerregaard and J. Sparso, "A router architecture for connectionoriented service guarantees in the MANGO clockless network-on-chip," in Proc. Des., Autom. Test Eur. Conf., Mar. 2005, pp. 1226-1231. (Pubitemid 44172177)
    • (2005) Proceedings -Design, Automation and Test in Europe, DATE '05 , vol.II , pp. 1226-1231
    • Bjerregaard, T.1    Sparso, J.2
  • 21
    • 33745800231 scopus 로고    scopus 로고
    • A survey of research and practices of network-on-chip
    • Mar.
    • T. Bjerregaard and S. Mahadevan, "A survey of research and practices of network-on-chip," ACM Comput. Surv., vol. 38, no. 1, pp. 1-51, Mar. 2006.
    • (2006) ACM Comput. Surv. , vol.38 , Issue.1 , pp. 1-51
    • Bjerregaard, T.1    Mahadevan, S.2
  • 23
    • 34250882322 scopus 로고    scopus 로고
    • Stochastic communication: A new paradigm for fault-tolerant networks-on-chip
    • Feb.
    • P. Bogdan, T. Dumitras, and R. Marculescu, "Stochastic communication: A new paradigm for fault-tolerant networks-on-chip," Hindawi VLSI Design, Feb. 2007.
    • (2007) Hindawi VLSI Design
    • Bogdan, P.1    Dumitras, T.2    Marculescu, R.3
  • 24
    • 1242309790 scopus 로고    scopus 로고
    • QNoC: QoS architecture and design process for network on chip
    • Feb.
    • E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, "QNoC: QoS architecture and design process for network on chip," J. Syst. Architecture: EUROMICRO J., vol. 50, no. 2/3, pp. 105-128, Feb. 2004.
    • (2004) J. Syst. Architecture: EUROMICRO J. , vol.50 , Issue.2-3 , pp. 105-128
    • Bolotin, E.1    Cidon, I.2    Ginosar, R.3    Kolodny, A.4
  • 27
    • 34047144470 scopus 로고    scopus 로고
    • GALS networks on chip: A new solution for asynchronous delay-insensitive links
    • Mar.
    • G. Campobello, M. Castano, C. Ciofi, and D. Mangano, "GALS networks on chip: A new solution for asynchronous delay-insensitive links," in Proc. Des., Autom. Test Eur. Conf., Mar. 2006, pp. 160-165.
    • (2006) Proc. Des., Autom. Test Eur. Conf. , pp. 160-165
    • Campobello, G.1    Castano, M.2    Ciofi, C.3    Mangano, D.4
  • 30
    • 33751400283 scopus 로고    scopus 로고
    • NoCEE: Energy macro-model extraction methodology for network on chip routers
    • Nov.
    • J. Chan and S. Parameswaran, "NoCEE: Energy macro-model extraction methodology for network on chip routers," in Proc. Int. Conf. Comput.- Aided Des., Nov. 2005, pp. 254-259.
    • (2005) Proc. Int. Conf. Comput.- Aided Des. , pp. 254-259
    • Chan, J.1    Parameswaran, S.2
  • 32
  • 33
    • 0034853842 scopus 로고    scopus 로고
    • Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
    • Jun.
    • T. Chelcea and S. M. Nowick, "Robust interfaces for mixed-timing systems with application to latency-insensitive protocols," in Proc. Des. Autom. Conf., Jun. 2001, pp. 21-26.
    • (2001) Proc. Des. Autom. Conf. , pp. 21-26
    • Chelcea, T.1    Nowick, S.M.2
  • 34
    • 1542269364 scopus 로고    scopus 로고
    • Leakage power modeling and optimization in interconnection networks
    • Aug.
    • X. Chen and L. Peh, "Leakage power modeling and optimization in interconnection networks," in Proc. Int. Symp. Low Power Electron. Des., Aug. 2003, pp. 90-95.
    • (2003) Proc. Int. Symp. Low Power Electron. Des. , pp. 90-95
    • Chen, X.1    Peh, L.2
  • 35
    • 52649098977 scopus 로고    scopus 로고
    • Energy-and performance-aware incremental mapping for networks on chip with multiple voltage levels
    • Oct.
    • C.-L. Chou and R. Marculescu, "Energy-and performance-aware incremental mapping for networks on chip with multiple voltage levels," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 27, no. 10, pp. 1866-1879, Oct. 2008.
    • (2008) IEEE Trans. Comput.-aided Design Integr. Circuits Syst. , vol.27 , Issue.10 , pp. 1866-1879
    • Chou, C.-L.1    Marculescu, R.2
  • 36
    • 84878634758 scopus 로고
    • Performance analysis of wormhole switching with adaptive routing in a two-dimensional torus
    • 1999
    • M. Colajanni, B. Ciciani, and F. Quaglia, "Performance analysis of wormhole switching with adaptive routing in a two-dimensional torus," in Proc. Int. Eur.-Par Conf. Parallel Process., 1999, vol. 1685, pp. 165-172.
    • (1685) Proc. Int. Eur.-par Conf. Parallel Process. , pp. 165-172
    • Colajanni, M.1    Ciciani, B.2    Quaglia, F.3
  • 40
    • 0034848112 scopus 로고    scopus 로고
    • Route packets, not wires: On-chip interconnection networks
    • Jun.
    • W. Dally and B. Towles, "Route packets, not wires: On-chip interconnection networks," in Proc. Des. Autom. Conf., Jun. 2001, pp. 684-689.
    • (2001) Proc. Des. Autom. Conf. , pp. 684-689
    • Dally, W.1    Towles, B.2
  • 41
    • 0026825968 scopus 로고
    • Virtual-channel flow control
    • Mar.
    • W. J. Dally, "Virtual-channel flow control," IEEE Trans. Parallel Distrib. Syst., vol. 3, no. 2, pp. 194-205, Mar. 1992.
    • (1992) IEEE Trans. Parallel Distrib. Syst. , vol.3 , Issue.2 , pp. 194-205
    • Dally, W.J.1
  • 44
    • 43949160401 scopus 로고
    • A comprehensive analytical model for wormhole routing in multicomputer systems
    • Nov.
    • J. Draper and J. Ghosh, "A comprehensive analytical model for wormhole routing in multicomputer systems," J. Parallel Distrib. Comput., vol. 23, no. 2, pp. 202-214, Nov. 1994.
    • (1994) J. Parallel Distrib. Comput. , vol.23 , Issue.2 , pp. 202-214
    • Draper, J.1    Ghosh, J.2
  • 46
    • 24144487243 scopus 로고    scopus 로고
    • A new scalable and cost-effective congestion management strategy for lossless multistage interconnection networks
    • Feb.
    • J. Duato et al., "A new scalable and cost-effective congestion management strategy for lossless multistage interconnection networks," in Proc. Int. Symp. High-Performance Comput. Architecture, Feb. 2005, pp. 108-119.
    • (2005) Proc. Int. Symp. High-performance Comput. Architecture , pp. 108-119
    • Duato, J.1
  • 49
    • 52649171528 scopus 로고    scopus 로고
    • Virtual circuit tree multicasting: A case for on-chip hardware multicast support
    • Jun.
    • N. Enright-Jerger, L.-S. Peh, and M. Lipasti, "Virtual circuit tree multicasting: A case for on-chip hardware multicast support," in Proc. Int. Symp. Comput. Architecture, Jun. 2008, pp. 229-240.
    • (2008) Proc. Int. Symp. Comput. Architecture , pp. 229-240
    • Enright-Jerger, N.1    Peh, L.-S.2    Lipasti, M.3
  • 50
    • 34548318954 scopus 로고    scopus 로고
    • Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks
    • Apr.
    • A. Ejlali, B. M. Al-Hashimi, P. Rosinger, and S. G. Miremadi, "Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks," in Proc. Des., Autom. Test Eur. Conf., Apr. 2007, pp. 1647-1652.
    • (2007) Proc. Des., Autom. Test Eur. Conf. , pp. 1647-1652
    • Ejlali, A.1    Al-Hashimi, B.M.2    Rosinger, P.3    Miremadi, S.G.4
  • 52
    • 27944486797 scopus 로고    scopus 로고
    • Frequency-based code placement for embedded multiprocessors
    • Jul.
    • C. M. Goldfeder, "Frequency-based code placement for embedded multiprocessors," in Proc. Des. Autom. Conf., Jul. 2005, pp. 696-699.
    • (2005) Proc. Des. Autom. Conf. , pp. 696-699
    • Goldfeder, C.M.1
  • 57
    • 0034878371 scopus 로고    scopus 로고
    • Hard real-time scheduling for low-energy using stochastic data and DVS processors
    • Aug.
    • F. Gruian, "Hard real-time scheduling for low-energy using stochastic data and DVS processors," in Proc. Int. Symp. Low-Power Electron. Des., Aug. 2001, pp. 46-51.
    • (2001) Proc. Int. Symp. Low-power Electron. Des. , pp. 46-51
    • Gruian, F.1
  • 59
    • 34548306710 scopus 로고    scopus 로고
    • Undisrupted quality-ofservice during reconfiguration of multiple applications in networks on chip
    • Apr.
    • A. Hansson, M. Coenen, and K. Goossens, "Undisrupted quality-ofservice during reconfiguration of multiple applications in networks on chip," in Proc. Des., Autom. Test Eur. Conf., Apr. 2007, pp. 954-959.
    • (2007) Proc. Des., Autom. Test Eur. Conf. , pp. 954-959
    • Hansson, A.1    Coenen, M.2    Goossens, K.3
  • 60
    • 34347259951 scopus 로고    scopus 로고
    • A unified approach to mapping and routing on a network-on-chip for both best-effort and guaranteed service traffic
    • May
    • A. Hansson, K. Goossens, and A. Radulescu, "A unified approach to mapping and routing on a network-on-chip for both best-effort and guaranteed service traffic," Hindawi VLSI Design, May 2007.
    • (2007) Hindawi VLSI Design
    • Hansson, A.1    Goossens, K.2    Radulescu, A.3
  • 61
    • 33750906036 scopus 로고    scopus 로고
    • Quantitative modeling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip
    • May
    • M. Harmanci, N. Escudero, Y. Leblebici, and P. Ienne, "Quantitative modeling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip," in Proc. Int. Symp. Circuits Syst., May 2005, pp. 1782-1785.
    • (2005) Proc. Int. Symp. Circuits Syst. , pp. 1782-1785
    • Harmanci, M.1    Escudero, N.2    Leblebici, Y.3    Ienne, P.4
  • 62
    • 2342622625 scopus 로고    scopus 로고
    • On-chip networks: A scalable, communication-centric embedded system design paradigm
    • Jan.
    • J. Henkel, W. Wolf, and S. Chakradhar, "On-chip networks: A scalable, communication-centric embedded system design paradigm," in Proc. VLSI Des., Jan. 2004, pp. 845-851.
    • (2004) Proc. VLSI Des. , pp. 845-851
    • Henkel, J.1    Wolf, W.2    Chakradhar, S.3
  • 63
    • 84955516546 scopus 로고    scopus 로고
    • A methodology for designing efficient on-chip interconnects on well-behaved communication patterns
    • Feb.
    • W. H. Ho and T. M. Pinkston, "A methodology for designing efficient on-chip interconnects on well-behaved communication patterns," in Proc. Int. Symp. High-Performance Comput. Architecture, Feb. 2003, pp. 377-388.
    • (2003) Proc. Int. Symp. High-performance Comput. Architecture , pp. 377-388
    • Ho, W.H.1    Pinkston, T.M.2
  • 64
    • 33646922057 scopus 로고    scopus 로고
    • The future of wires
    • Apr.
    • M. Horowitz, R. Ho, and K. Mai, "The future of wires," Proc. IEEE, vol. 89, no. 4, pp. 490-504, Apr. 2001.
    • (2001) Proc. IEEE , vol.89 , Issue.4 , pp. 490-504
    • Horowitz, M.1    Ho, R.2    Mai, K.3
  • 66
    • 38349147091 scopus 로고    scopus 로고
    • An analytical model for wormhole routing with finite size input buffers
    • Jun.
    • P. Hu and L. Kleinrock, "An analytical model for wormhole routing with finite size input buffers," in Proc. 15th Int. Teletraffic Congr., Jun. 1997, pp. 549-560.
    • (1997) Proc. 15th Int. Teletraffic Congr. , pp. 549-560
    • Hu, P.1    Kleinrock, L.2
  • 67
    • 84954421164 scopus 로고    scopus 로고
    • Energy-aware mapping for tile-based NOC architectures under performance constraints
    • Kitakyushu, Japan, Jan.
    • J. Hu and R. Marculescu, "Energy-aware mapping for tile-based NOC architectures under performance constraints," in Proc. Asia South Pacific Des. Autom. Conf., Kitakyushu, Japan, Jan. 2003, pp. 233-239.
    • (2003) Proc. Asia South Pacific Des. Autom. Conf. , pp. 233-239
    • Hu, J.1    Marculescu, R.2
  • 68
    • 24944436640 scopus 로고    scopus 로고
    • Communication and task scheduling of application-specific networks-on-chip
    • Sep.
    • J. Hu and R. Marculescu, "Communication and task scheduling of application-specific networks-on-chip," Proc. Inst. Elect. Eng. - Comput. Digit. Tech., vol. 152, no. 5, pp. 643-651, Sep. 2005.
    • (2005) Proc. Inst. Elect. Eng. - Comput. Digit. Tech. , vol.152 , Issue.5 , pp. 643-651
    • Hu, J.1    Marculescu, R.2
  • 69
    • 4444324957 scopus 로고    scopus 로고
    • DyAD - Smart routing for networks-onchip
    • Jun.
    • J. Hu and R. Marculescu, "DyAD - Smart routing for networks-onchip," in Proc. Des. Autom. Conf., Jun. 2004, pp. 260-263.
    • (2004) Proc. Des. Autom. Conf. , pp. 260-263
    • Hu, J.1    Marculescu, R.2
  • 70
    • 16444383201 scopus 로고    scopus 로고
    • Energy-and performance-aware mapping for regular NoC architectures
    • Apr.
    • J. Hu and R. Marculescu, "Energy-and performance-aware mapping for regular NoC architectures," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 4, pp. 551-562, Apr. 2005.
    • (2005) IEEE Trans. Comput.-aided Design Integr. Circuits Syst. , vol.24 , Issue.4 , pp. 551-562
    • Hu, J.1    Marculescu, R.2
  • 71
    • 33845651403 scopus 로고    scopus 로고
    • System-level buffer allocation for application-specific networks-on-chip router design
    • Dec.
    • J. Hu, U. Y. Ogras, and R. Marculescu, "System-level buffer allocation for application-specific networks-on-chip router design," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 25, no. 12, pp. 2919-2933, Dec. 2006.
    • (2006) IEEE Trans. Comput.-aided Design Integr. Circuits Syst. , vol.25 , Issue.12 , pp. 2919-2933
    • Hu, J.1    Ogras, U.Y.2    Marculescu, R.3
  • 72
    • 17644418462 scopus 로고    scopus 로고
    • Thermal-aware IP virtualization and placement for networks-on-chip architecture
    • W. Hung et al., "Thermal-aware IP virtualization and placement for networks-on-chip architecture," in Proc. Int. Conf. Comput. Des., 2004, pp. 430-437.
    • (2004) Proc. Int. Conf. Comput. Des. , pp. 430-437
    • Hung, W.1
  • 73
    • 33748555522 scopus 로고    scopus 로고
    • Correlation between detailed and simplified simulations in studying multiprocessor architecture
    • Oct.
    • K. Z. Ibrahim, "Correlation between detailed and simplified simulations in studying multiprocessor architecture," in Proc. Int. Conf. Comput. Des., Oct. 2005, pp. 387-392.
    • (2005) Proc. Int. Conf. Comput. Des. , pp. 387-392
    • Ibrahim, K.Z.1
  • 74
    • 0042111484 scopus 로고    scopus 로고
    • A. Jantsch and H. Tenhunen, Eds. Norwell, MA: Kluwer
    • Networks-on-Chip, A. Jantsch and H. Tenhunen, Eds. Norwell, MA: Kluwer, 2003.
    • (2003) Networks-on-chip
  • 75
    • 33745715755 scopus 로고    scopus 로고
    • Power analysis of link level and end-to-end data protection in networks on chip
    • May
    • A. Jantsch, R. Lauter, and A. Vitkowski, "Power analysis of link level and end-to-end data protection in networks on chip," in Proc. Int. Symp. Circuits Syst., May 2005, pp. 1770-1773.
    • (2005) Proc. Int. Symp. Circuits Syst. , pp. 1770-1773
    • Jantsch, A.1    Lauter, R.2    Vitkowski, A.3
  • 76
    • 27844556591 scopus 로고    scopus 로고
    • Near speed-of-light onchip interconnects using pulsed current-mode signalling
    • Jun.
    • A. P. Jose, G. Patounakis, and K. L. Shepard, "Near speed-of-light onchip interconnects using pulsed current-mode signalling," in Proc. Symp. VLSI Circuits, Jun. 2005, pp. 108-111.
    • (2005) Proc. Symp. VLSI Circuits , pp. 108-111
    • Jose, A.P.1    Patounakis, G.2    Shepard, K.L.3
  • 77
    • 0037969184 scopus 로고    scopus 로고
    • A wire-delay scalable microprocessor architecture for high performance systems
    • Feb.
    • S. W. Keckler et al., "A wire-delay scalable microprocessor architecture for high performance systems," in Proc. Solid-State Circuits Conf., Feb. 2003, pp. 168-169.
    • (2003) Proc. Solid-state Circuits Conf. , pp. 168-169
    • Keckler, S.W.1
  • 78
    • 50249133214 scopus 로고    scopus 로고
    • Equalized interconnects for on-chip networks: Modeling and optimization framework
    • Nov.
    • B. Kim and V. Stojanovic, "Equalized interconnects for on-chip networks: Modeling and optimization framework," in Proc. Int. Conf. Comput.-Aided Des., Nov. 2007, pp. 552-559.
    • (2007) Proc. Int. Conf. Comput.-aided Des. , pp. 552-559
    • Kim, B.1    Stojanovic, V.2
  • 79
    • 36348960161 scopus 로고    scopus 로고
    • Solutions for real chip implementation issues of NoC and their application to memory-centric NoC
    • May
    • D. Kim, K. Kim, J. Kim, S. Lee, and H. Yoo, "Solutions for real chip implementation issues of NoC and their application to memory-centric NoC," in Proc. Int. Symp. Netw.-on-Chips, May 2007, pp. 30-39.
    • (2007) Proc. Int. Symp. Netw.-on-chips , pp. 30-39
    • Kim, D.1    Kim, K.2    Kim, J.3    Lee, S.4    Yoo, H.5
  • 80
    • 1542299255 scopus 로고    scopus 로고
    • Energy optimization techniques in cluster interconnects
    • Aug.
    • E. J. Kim et al., "Energy optimization techniques in cluster interconnects," in Proc. Int. Symp. Low Power Electron. Des., Aug. 2003, pp. 459-464.
    • (2003) Proc. Int. Symp. Low Power Electron. Des. , pp. 459-464
    • Kim, E.J.1
  • 85
    • 35348908288 scopus 로고    scopus 로고
    • A novel dimensionally-decomposed router for on-chip communication in 3D architectures
    • Jun.
    • J. Kim et al., "A novel dimensionally-decomposed router for on-chip communication in 3D architectures," in Proc. Int. Symp. Comput. Architecture, Jun. 2007, pp. 138-149.
    • (2007) Proc. Int. Symp. Comput. Architecture , pp. 138-149
    • Kim, J.1
  • 86
    • 35348835387 scopus 로고    scopus 로고
    • Flattened butterfly: A costefficient topology for high-radix networks
    • Jun.
    • J. Kim, W. J. Dally, and D. Abts, "Flattened butterfly: A costefficient topology for high-radix networks," in Proc. Int. Symp. Comput. Architecture, Jun. 2007, pp. 126-137.
    • (2007) Proc. Int. Symp. Comput. Architecture , pp. 126-137
    • Kim, J.1    Dally, W.J.2    Abts, D.3
  • 87
    • 1142299901 scopus 로고    scopus 로고
    • A modular simulation framework for architectural exploration of on-chip interconnection networks
    • Oct.
    • T. Kogel et al., "A modular simulation framework for architectural exploration of on-chip interconnection networks," in Proc. Int. Conf. Hardware-Software Codesign Syst. Synthesis, Oct. 2003, pp. 7-12.
    • (2003) Proc. Int. Conf. Hardware-software Codesign Syst. Synthesis , pp. 7-12
    • Kogel, T.1
  • 88
    • 35348858651 scopus 로고    scopus 로고
    • Express virtual channels: Towards the ideal interconnection fabric
    • Jun.
    • A. Kumar, L. Peh, P. Kundu, and N. K. Jha, "Express virtual channels: Towards the ideal interconnection fabric," in Proc. Int. Symp. Comput. Architecture, Jun. 2007, pp. 150-161.
    • (2007) Proc. Int. Symp. Comput. Architecture , pp. 150-161
    • Kumar, A.1    Peh, L.2    Kundu, P.3    Jha, N.K.4
  • 89
    • 27544456315 scopus 로고    scopus 로고
    • Interconnections in multicore architectures: Understanding mechanisms, overheads and scaling
    • Jun.
    • R. Kumar, V. Zyuban, and D. M. Tullsen, "Interconnections in multicore architectures: Understanding mechanisms, overheads and scaling," in Proc. Int. Symp. Comput. Architecture, Jun. 2005, pp. 408-419.
    • (2005) Proc. Int. Symp. Comput. Architecture , pp. 408-419
    • Kumar, R.1    Zyuban, V.2    Tullsen, D.M.3
  • 90
    • 0034995968 scopus 로고    scopus 로고
    • Evaluation of the traffic-performance characteristics of system-on-chip communication architectures
    • Oct.
    • K. Lahiri et al., "Evaluation of the traffic-performance characteristics of system-on-chip communication architectures," in Proc. Int. Conf. VLSI Des., Oct. 2000, pp. 29-35.
    • (2000) Proc. Int. Conf. VLSI Des. , pp. 29-35
    • Lahiri, K.1
  • 91
    • 34548254878 scopus 로고    scopus 로고
    • On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus and network-on-chip approaches
    • Aug.
    • H. G. Lee, N. Chang, U. Y. Ogras, and R. Marculescu, "On-chip communication architecture exploration: A quantitative evaluation of point-to-point, bus and network-on-chip approaches," ACM Trans. Des. Autom. Electron. Syst., vol. 12, no. 3, pp. 1-20, Aug. 2007.
    • (2007) ACM Trans. Des. Autom. Electron. Syst. , vol.12 , Issue.3 , pp. 1-20
    • Lee, H.G.1    Chang, N.2    Ogras, U.Y.3    Marculescu, R.4
  • 92
    • 52649094492 scopus 로고    scopus 로고
    • Globally-synchronized frames for guaranteed quality-of-service in on-chip networks
    • J. W. Lee, A. Ng, and K. Asanovic, "Globally-synchronized frames for guaranteed quality-of-service in on-chip networks," in Proc. Int. Symp. Comput. Architecture, 2008, pp. 89-100.
    • (2008) Proc. Int. Symp. Comput. Architecture , pp. 89-100
    • Lee, J.W.1    Ng, A.2    Asanovic, K.3
  • 93
    • 2442698800 scopus 로고    scopus 로고
    • A 51 mW 1.6 GHz on-chip network for low-power heterogeneous SoC platform
    • Feb.
    • K. Lee et al., "A 51 mW 1.6 GHz on-chip network for low-power heterogeneous SoC platform," in Proc. Int. Solid-State Circuits Conf., Feb. 2004, pp. 152-518.
    • (2004) Proc. Int. Solid-state Circuits Conf. , pp. 152-518
    • Lee, K.1
  • 95
    • 34547159402 scopus 로고    scopus 로고
    • Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems
    • Jul.
    • L. F. Leung and C. Y. Tsui, "Optimal link scheduling on improving best-effort and guaranteed services performance in network-on-chip systems," in Proc. Des. Autom. Conf., Jul. 2006, pp. 833-838.
    • (2006) Proc. Des. Autom. Conf. , pp. 833-838
    • Leung, L.F.1    Tsui, C.Y.2
  • 96
    • 33751432061 scopus 로고    scopus 로고
    • Compiler-directed voltage scaling on communication links for reducing power consumption
    • F. Li, G. Chen, and M. Kandemir, "Compiler-directed voltage scaling on communication links for reducing power consumption," in Proc. Int. Conf. Comput.-Aided Des., 2005, pp. 456-460.
    • (2005) Proc. Int. Conf. Comput.-aided Des. , pp. 456-460
    • Li, F.1    Chen, G.2    Kandemir, M.3
  • 98
    • 0036916225 scopus 로고    scopus 로고
    • Throughput-driven IC communication fabric synthesis
    • T. Lin and L. T. Pileggi, "Throughput-driven IC communication fabric synthesis," in Proc. Int. Conf. Comput.-Aided Des., 2002, pp. 274-279.
    • (2002) Proc. Int. Conf. Comput.-aided Des. , pp. 274-279
    • Lin, T.1    Pileggi, L.T.2
  • 99
    • 84886567968 scopus 로고    scopus 로고
    • Power-aware test scheduling in network-on-chip using variable-rate on-chip clocking
    • May
    • C. Liu, J. Shi, E. Cota, and V. Iyengar, "Power-aware test scheduling in network-on-chip using variable-rate on-chip clocking," in Proc. VLSI Test Symp., May 2005, pp. 349-354.
    • (2005) Proc. VLSI Test Symp. , pp. 349-354
    • Liu, C.1    Shi, J.2    Cota, E.3    Iyengar, V.4
  • 100
    • 34547268960 scopus 로고    scopus 로고
    • Layered switching for networks on chip
    • Jun.
    • Z. Lu, M. Liu, and A. Jantsch, "Layered switching for networks on chip," in Proc. Des. Autom. Conf., Jun. 2007, pp. 122-127.
    • (2007) Proc. Des. Autom. Conf. , pp. 122-127
    • Lu, Z.1    Liu, M.2    Jantsch, A.3
  • 101
    • 0034477891 scopus 로고    scopus 로고
    • Power-conscious joint scheduling of periodic task graphs and aperiodic tasks in distributed real-time embedded systems
    • Nov.
    • J. Luo and N. K. Jha, "Power-conscious joint scheduling of periodic task graphs and aperiodic tasks in distributed real-time embedded systems," in Proc. Int. Conf. Comput.-Aided Des., Nov. 2000, pp. 357-364.
    • (2000) Proc. Int. Conf. Comput.-aided Des. , pp. 357-364
    • Luo, J.1    Jha, N.K.2
  • 105
    • 27944452666 scopus 로고    scopus 로고
    • Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC
    • Jul.
    • S. Manolache, P. Eles, and Z. Peng, "Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC," in Proc. Des. Autom. Conf., Jul. 2005, pp. 266-269.
    • (2005) Proc. Des. Autom. Conf. , pp. 266-269
    • Manolache, S.1    Eles, P.2    Peng, Z.3
  • 106
    • 34547326027 scopus 로고    scopus 로고
    • Introducing the superGT network-onchip
    • Jun.
    • T. Marescaux and H. Corporaal, "Introducing the superGT network-onchip," in Proc. Des. Autom. Conf., Jun. 2007, pp. 116-121.
    • (2007) Proc. Des. Autom. Conf. , pp. 116-121
    • Marescaux, T.1    Corporaal, H.2
  • 107
    • 35348925935 scopus 로고    scopus 로고
    • G. De Micheli and L. Benini, Eds. San Mateo, CA: Morgan Kaufmann
    • Networks on Chips: Technology and Tools, G. De Micheli and L. Benini, Eds. San Mateo, CA: Morgan Kaufmann, 2006.
    • (2006) Networks on Chips: Technology and Tools
  • 108
    • 3042740415 scopus 로고    scopus 로고
    • Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip
    • Feb.
    • M. Millberg, E. Nilsson, R. Thid, and A. Jantsch, "Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip," in Proc. Des., Autom. Test Eur. Conf., Feb. 2004, pp. 890-895.
    • (2004) Proc. Des., Autom. Test Eur. Conf. , pp. 890-895
    • Millberg, M.1    Nilsson, E.2    Thid, R.3    Jantsch, A.4
  • 109
    • 84947288173 scopus 로고    scopus 로고
    • Energy aware scheduling for distributed realtime systems
    • Apr.
    • R. Mishra et al., "Energy aware scheduling for distributed realtime systems," in Proc. Int. Parallel Distrib. Process. Symp., Apr. 2003, p. 12b.
    • (2003) Proc. Int. Parallel Distrib. Process. Symp.
    • Mishra, R.1
  • 111
    • 34247220407 scopus 로고    scopus 로고
    • A method for routing packets across multiple paths in NoCs with in-order delivery and fault-tolerance guarantees
    • May
    • S. Murali, D. Atienza, L. Benini, and G. De Micheli, "A method for routing packets across multiple paths in NoCs with in-order delivery and fault-tolerance guarantees," Hindawi VLSI Design, May 2007.
    • (2007) Hindawi VLSI Design
    • Murali, S.1    Atienza, D.2    Benini, L.3    De Micheli, G.4
  • 112
    • 27344448860 scopus 로고    scopus 로고
    • Analysis of error recovery schemes for networks on chip
    • Sep./ Oct.
    • S. Murali et al., "Analysis of error recovery schemes for networks on chip," IEEE Des. Test. Comput., vol. 22, no. 5, pp. 434-442, Sep./ Oct. 2005.
    • (2005) IEEE Des. Test. Comput. , vol.22 , Issue.5 , pp. 434-442
    • Murali, S.1
  • 114
    • 46149088969 scopus 로고    scopus 로고
    • Designing application-specific networks on chips with floorplan information
    • Nov.
    • S. Murali et al., "Designing application-specific networks on chips with floorplan information," in Proc. Int. Conf. Comput.-Aided Des., Nov. 2006, pp. 355-362.
    • (2006) Proc. Int. Conf. Comput.-aided Des. , pp. 355-362
    • Murali, S.1
  • 115
    • 3042567207 scopus 로고    scopus 로고
    • Bandwidth-constrained mapping of cores onto NoC architectures
    • Feb.
    • S. Murali and G. De Micheli, "Bandwidth-constrained mapping of cores onto NoC architectures," in Proc. Des., Autom. Test Eur. Conf., Feb. 2004, pp. 896-901.
    • (2004) Proc. Des., Autom. Test Eur. Conf. , pp. 896-901
    • Murali, S.1    De Micheli, G.2
  • 116
    • 40349107206 scopus 로고    scopus 로고
    • ViChaR: A dynamic virtual channel regulator for network-on-chip routers
    • Dec.
    • C. A. Nicopoulos et al., "ViChaR: A dynamic virtual channel regulator for network-on-chip routers," in Proc. Int. Symp. Microarchitecture, Dec. 2006, pp. 333-346.
    • (2006) Proc. Int. Symp. Microarchitecture , pp. 333-346
    • Nicopoulos, C.A.1
  • 117
    • 34250792968 scopus 로고    scopus 로고
    • High-performance long NoC link using delayinsensitive current-mode signaling
    • Mar.
    • E. Nigussie et al., "High-performance long NoC link using delayinsensitive current-mode signaling," Hindawi VLSI Design - Special Issue on Networks-on-Chip, vol. 2007, Mar. 2007.
    • (2007) Hindawi VLSI Design - Special Issue on Networks-on-chip , vol.2007
    • Nigussie, E.1
  • 118
    • 84893736605 scopus 로고    scopus 로고
    • Load distribution with the proximity congestion awareness in a network on chip
    • Mar.
    • E. Nilsson, M. Millberg, J. Oberg, and A. Jantsch, "Load distribution with the proximity congestion awareness in a network on chip," in Proc. Des., Autom. Test Eur. Conf., Mar. 2003, pp. 1126-1127.
    • (2003) Proc. Des., Autom. Test Eur. Conf. , pp. 1126-1127
    • Nilsson, E.1    Millberg, M.2    Oberg, J.3    Jantsch, A.4
  • 119
    • 33646934107 scopus 로고    scopus 로고
    • Energy-and performance-driven NoC communication architecture synthesis using a decomposition approach
    • Mar.
    • U. Y. Ogras and R. Marculescu, "Energy-and performance-driven NoC communication architecture synthesis using a decomposition approach," in Proc. Des., Autom. Test Eur., Mar. 2005, pp. 352-357.
    • (2005) Proc. Des., Autom. Test Eur. , pp. 352-357
    • Ogras, U.Y.1    Marculescu, R.2
  • 122
    • 40049087837 scopus 로고    scopus 로고
    • Analysis and optimization of prediction-based flow control in networks-on-chip
    • Jan.
    • U. Y. Ogras and R. Marculescu, "Analysis and optimization of prediction-based flow control in networks-on-chip," ACM Trans. Des. Autom. Electron. Syst., vol. 13, no. 1, pp. 1-28, Jan. 2008.
    • (2008) ACM Trans. Des. Autom. Electron. Syst. , vol.13 , Issue.1 , pp. 1-28
    • Ogras, U.Y.1    Marculescu, R.2
  • 123
    • 34548304654 scopus 로고    scopus 로고
    • Analytical router modeling for networks-on-chip performance analysis
    • Apr.
    • U. Y. Ogras and R. Marculescu, "Analytical router modeling for networks-on-chip performance analysis," in Proc. Des., Autom. Test Eur. Conf., Apr. 2007, pp. 1096-1101.
    • (2007) Proc. Des., Autom. Test Eur. Conf. , pp. 1096-1101
    • Ogras, U.Y.1    Marculescu, R.2
  • 126
    • 34248557637 scopus 로고    scopus 로고
    • PIRATE: A framework for power/ performance exploration of network-on-chip architectures
    • Sep.
    • G. Palermo and C. Silvano, "PIRATE: A framework for power/ performance exploration of network-on-chip architectures," in Proc. Int. Workshop Power Timing Model., Optimization Simul., Sep. 2004, pp. 521-531.
    • (2004) Proc. Int. Workshop Power Timing Model., Optimization Simul. , pp. 521-531
    • Palermo, G.1    Silvano, C.2
  • 127
    • 10444263106 scopus 로고    scopus 로고
    • Layout, performance and power trade-offs in mesh-based network-on-chip architectures
    • Dec.
    • D. Pamunuwa et al., "Layout, performance and power trade-offs in mesh-based network-on-chip architectures," in Proc. IFIP Int. Conf. Very Large Scale Integr., Dec. 2003, p. 362.
    • (2003) Proc. IFIP Int. Conf. Very Large Scale Integr. , pp. 362
    • Pamunuwa, D.1
  • 128
    • 24144461667 scopus 로고    scopus 로고
    • Performance evaluation and design trade-offs for network-on-chip interconnect architectures
    • Aug.
    • P. P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, "Performance evaluation and design trade-offs for network-on-chip interconnect architectures," IEEE Trans. Comput., vol. 54, no. 8, pp. 1025-1040, Aug. 2005.
    • (2005) IEEE Trans. Comput. , vol.54 , Issue.8 , pp. 1025-1040
    • Pande, P.P.1    Grecu, C.2    Jones, M.3    Ivanov, A.4    Saleh, R.5
  • 129
    • 0002017054 scopus 로고
    • The quadratic assignment problem: A survey and recent developments
    • P. Pardalos and H. Wolkowicz, Eds., DIMACS Series in Discrete Mathematics and Theoretical Computer Science
    • P. M. Pardalos, F. Rendl, and H. Wolkowicz, "The quadratic assignment problem: A survey and recent developments," in Proc. DIMACS Workshop, P. Pardalos and H. Wolkowicz, Eds., DIMACS Series in Discrete Mathematics and Theoretical Computer Science, 1994, vol. 16, pp. 1-42.
    • (1994) Proc. DIMACS Workshop , vol.16 , pp. 1-42
    • Pardalos, P.M.1    Rendl, F.2    Wolkowicz, H.3
  • 130
    • 84941162557 scopus 로고    scopus 로고
    • Self-similar network traffic: An overview
    • K. Park and W. Willinger, Eds. New York: Wiley-Interscience
    • K. Park and W.Willinger, "Self-similar network traffic: An overview," in Self-Similar Network Traffic and Performance Evaluation, K. Park and W. Willinger, Eds. New York: Wiley-Interscience, 1999.
    • (1999) Self-similar Network Traffic and Performance Evaluation
    • Park, K.1    Willinger, W.2
  • 136
    • 27344435504 scopus 로고    scopus 로고
    • The design and implementation of a first-generation CELL processor
    • Feb.
    • D. Pham et al., "The design and implementation of a first-generation CELL processor," in Proc. Solid-State Circuits Conf., Feb. 2005, pp. 184-592.
    • (2005) Proc. Solid-state Circuits Conf. , pp. 184-592
    • Pham, D.1
  • 142
  • 143
    • 85013625412 scopus 로고    scopus 로고
    • Iterative schedule optimization for voltage scalable distributed embedded systems
    • Feb. DOI=http://doi.acm.org/10.1145/972627.972636
    • M. T. Schmitz, B. M. Al-Hashimi, and P. Eles, "Iterative schedule optimization for voltage scalable distributed embedded systems," ACM Trans. Embedd. Comput. Syst., vol. 3, no. 1, pp. 182-217, Feb. 2004. DOI=http://doi.acm.org/10.1145/972627.972636.
    • (2004) ACM Trans. Embedd. Comput. Syst. , vol.3 , Issue.1 , pp. 182-217
    • Schmitz, M.T.1    Al-Hashimi, B.M.2    Eles, P.3
  • 145
    • 84955452760 scopus 로고    scopus 로고
    • Dynamic voltage scaling with links for power optimization of interconnection networks
    • Jan.
    • L. Shang, L. Peh, and N. K. Jha, "Dynamic voltage scaling with links for power optimization of interconnection networks," in Proc. Int. Symp. High-Performance Comput. Architecture, Jan. 2003, pp. 91-102.
    • (2003) Proc. Int. Symp. High-performance Comput. Architecture , pp. 91-102
    • Shang, L.1    Peh, L.2    Jha, N.K.3
  • 146
    • 21644444692 scopus 로고    scopus 로고
    • Thermal modeling, characterization and management of on-chip networks
    • Dec.
    • L. Shang, L. Peh, A. Kumar, and N. K. Jha, "Thermal modeling, characterization and management of on-chip networks," in Proc. Int. Symp. Microarchitecture, Dec. 2004, pp. 67-78.
    • (2004) Proc. Int. Symp. Microarchitecture , pp. 67-78
    • Shang, L.1    Peh, L.2    Kumar, A.3    Jha, N.K.4
  • 148
    • 34548316907 scopus 로고    scopus 로고
    • Systematic comparison between the asynchronous and the multi-synchronous implementations of a network-on-chip architecture
    • Apr.
    • A. Sheibanyrad, I. M. Panades, and A. Greiner, "Systematic comparison between the asynchronous and the multi-synchronous implementations of a network-on-chip architecture," in Proc. Des., Autom. Test Eur. Conf., Apr. 2007, pp. 1090-1095.
    • (2007) Proc. Des., Autom. Test Eur. Conf. , pp. 1090-1095
    • Sheibanyrad, A.1    Panades, I.M.2    Greiner, A.3
  • 149
    • 39749129856 scopus 로고    scopus 로고
    • Skewtolerant global synchronization based on periodically all-in-phase clocking for multi-core SOC platforms
    • Jun.
    • A. Shibayama, K. Nose, S. Torii, M. Mizuno, and M. Edahiro, "Skewtolerant global synchronization based on periodically all-in-phase clocking for multi-core SOC platforms," in Proc. Symp. VLSI Circuits, Jun. 2007, pp. 158-159.
    • (2007) Proc. Symp. VLSI Circuits , pp. 158-159
    • Shibayama, A.1    Nose, K.2    Torii, S.3    Mizuno, M.4    Edahiro, M.5
  • 150
    • 33746638860 scopus 로고    scopus 로고
    • Energy-efficient soft error-tolerant digital signal processing
    • Apr.
    • B. Shim and N. R. Shanbhag, "Energy-efficient soft error-tolerant digital signal processing," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 4, pp. 336-348, Apr. 2006.
    • (2006) IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol.14 , Issue.4 , pp. 336-348
    • Shim, B.1    Shanbhag, N.R.2
  • 151
    • 16244370420 scopus 로고    scopus 로고
    • Power-aware communication optimization for networks-on-chips with voltage scalable links
    • Sep.
    • D. Shin and J. Kim, "Power-aware communication optimization for networks-on-chips with voltage scalable links," in Proc. Int. Conf. Hardware/Softw. Codesign Syst. Synthesis, Sep. 2004, pp. 170-175.
    • (2004) Proc. Int. Conf. Hardware/Softw. Codesign Syst. Synthesis , pp. 170-175
    • Shin, D.1    Kim, J.2
  • 152
    • 0035279683 scopus 로고    scopus 로고
    • Intra-task voltage scheduling for low-energy hard real-time applications
    • DOI 10.1109/54.914596
    • D. Shin, J. Kim, and S. Lee, "Intra-task voltage scheduling for lowenergy hard real-time applications," IEEE Des. Test. Comput., vol. 18, no. 2, pp. 20-30, Mar./Apr. 2001. (Pubitemid 32293325)
    • (2001) IEEE Design and Test of Computers , vol.18 , Issue.2 , pp. 20-30
    • Shin, D.1    Kim, J.2    Lee, S.3
  • 154
    • 84893719539 scopus 로고    scopus 로고
    • Managing power consumption in networks on chips
    • Mar.
    • T. Simunic and S. Boyd, "Managing power consumption in networks on chips," in Proc. Des., Autom. Test Eur. Conf., Mar. 2002, pp. 110-116.
    • (2002) Proc. Des., Autom. Test Eur. Conf. , pp. 110-116
    • Simunic, T.1    Boyd, S.2
  • 155
    • 17644413857 scopus 로고    scopus 로고
    • Design space exploration of power-aware on/off interconnection networks
    • Oct.
    • V. Soteriou and L. Peh, "Design space exploration of power-aware on/off interconnection networks," in Proc. Int. Conf. Comput. Des., Oct. 2004, pp. 510-517.
    • (2004) Proc. Int. Conf. Comput. Des. , pp. 510-517
    • Soteriou, V.1    Peh, L.2
  • 157
    • 34548331522 scopus 로고    scopus 로고
    • A scalable, timingsafe, network-on-chip architecture with an integrated clock distribution method
    • Apr.
    • T. Sparso, M. B. Stensgaard, and J. Sparso, "A scalable, timingsafe, network-on-chip architecture with an integrated clock distribution method," in Proc. Des., Autom. Test Eur. Conf., Apr. 2007, pp. 648-653.
    • (2007) Proc. Des., Autom. Test Eur. Conf. , pp. 648-653
    • Sparso, T.1    Stensgaard, M.B.2    Sparso, J.3
  • 158
    • 28444439962 scopus 로고    scopus 로고
    • A technique for low energy mapping and routing in network-on-chip architectures
    • Aug.
    • K. Srinivasan and K. S. Chatha, "A technique for low energy mapping and routing in network-on-chip architectures," in Proc. Int. Symp. Low Power Electron. Des., Aug. 2005, pp. 387-392.
    • (2005) Proc. Int. Symp. Low Power Electron. Des. , pp. 387-392
    • Srinivasan, K.1    Chatha, K.S.2
  • 159
    • 33746590812 scopus 로고    scopus 로고
    • Linear programming based techniques for synthesis of network-on-chip architectures
    • Apr.
    • K. Srinivasan, K. S. Chatha, and G. Konjevod, "Linear programming based techniques for synthesis of network-on-chip architectures," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 14, no. 4, pp. 407-420, Apr. 2006.
    • (2006) IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol.14 , Issue.4 , pp. 407-420
    • Srinivasan, K.1    Chatha, K.S.2    Konjevod, G.3
  • 160
    • 34047167070 scopus 로고    scopus 로고
    • A low complexity heuristic for design of custom network-on-chip architectures
    • Mar.
    • K. Srinivasan and K. S. Chatha, "A low complexity heuristic for design of custom network-on-chip architectures," in Proc. Des., Autom. Test Eur. Conf., Mar. 2006, pp. 130-135.
    • (2006) Proc. Des., Autom. Test Eur. Conf. , pp. 130-135
    • Srinivasan, K.1    Chatha, K.S.2
  • 161
    • 42949086483 scopus 로고    scopus 로고
    • Resource-efficient routing and scheduling of time-constrained streaming communication on networks-on-chip
    • Mar.
    • S. Stuijk, T. Basten, M. Geilen, A. H. Ghamarian, and B. Theelen, "Resource-efficient routing and scheduling of time-constrained streaming communication on networks-on-chip," J. Syst. Architecture: EUROMICRO J., vol. 54, no. 3/4, pp. 411-426, Mar. 2008.
    • (2008) J. Syst. Architecture: EUROMICRO J. , vol.54 , Issue.3-4 , pp. 411-426
    • Stuijk, S.1    Basten, T.2    Geilen, M.3    Ghamarian, A.H.4    Theelen, B.5
  • 163
    • 0036505033 scopus 로고    scopus 로고
    • The RAW microprocessor: A computational fabric for software circuits and general-purpose programs
    • Mar./Apr.
    • M. B. Taylor et al., "The RAW microprocessor: A computational fabric for software circuits and general-purpose programs," IEEE Micro, vol. 22, no. 2, pp. 25-35, Mar./Apr. 2002.
    • (2002) IEEE Micro , vol.22 , Issue.2 , pp. 25-35
    • Taylor, M.B.1
  • 166
    • 34548858682 scopus 로고    scopus 로고
    • An 80-tile 1.28TFLOPS network-on-chip in 65 nm CMOS
    • Feb.
    • S. Vangal et al., "An 80-tile 1.28TFLOPS network-on-chip in 65 nm CMOS," in Proc. Solid-State Circuits Conf., Feb. 2007, pp. 98-589.
    • (2007) Proc. Solid-state Circuits Conf. , pp. 98-589
    • Vangal, S.1
  • 167
    • 1342329326 scopus 로고    scopus 로고
    • On-chip traffic modeling and synthesis for MPEG-2 video applications
    • Jan.
    • G. Varatkar and R. Marculescu, "On-chip traffic modeling and synthesis for MPEG-2 video applications," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 12, no. 1, pp. 108-119, Jan. 2004.
    • (2004) IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , vol.12 , Issue.1 , pp. 108-119
    • Varatkar, G.1    Marculescu, R.2
  • 168
    • 56749092977 scopus 로고    scopus 로고
    • Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip
    • May
    • G. Varatkar, S. Narayanan, N. R. Shanbhag, and D. L. Jones, "Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip, " in Proc. ACM Great Lakes Symp. VLSI, May 2008, pp. 351-354.
    • (2008) Proc. ACM Great Lakes Symp. VLSI , pp. 351-354
    • Varatkar, G.1    Narayanan, S.2    Shanbhag, N.R.3    Jones, D.L.4
  • 169
    • 0346148453 scopus 로고    scopus 로고
    • Communication-aware task scheduling and voltage selection for total systems energy minimization
    • San Jose, CA, Nov.
    • G. Varatkar and R. Marculescu, "Communication-aware task scheduling and voltage selection for total systems energy minimization," in Proc. IEEE/ACM Int. Conf. Comput.-Aided Des., San Jose, CA, Nov. 2003, pp. 510-517.
    • (2003) Proc. IEEE/ACM Int. Conf. Comput.-aided Des. , pp. 510-517
    • Varatkar, G.1    Marculescu, R.2
  • 170
    • 84862144932 scopus 로고    scopus 로고
    • Power-driven design of router microarchitectures in on-chip networks
    • Nov.
    • H. Wang, L. Peh, and S. Malik, "Power-driven design of router microarchitectures in on-chip networks," in Proc. Int. Symp. Microarchitecture, Nov. 2003, pp. 105-116.
    • (2003) Proc. Int. Symp. Microarchitecture , pp. 105-116
    • Wang, H.1    Peh, L.2    Malik, S.3
  • 171
    • 33645002018 scopus 로고    scopus 로고
    • A technology-aware and energy-oriented topology exploration for on-chip networks
    • DOI 10.1109/DATE.2005.40, 1395763, Proceedings - Design, Automation and Test in Europe, DATE '05
    • H. Wang, L. Peh, and S. Malik, "A technology-aware and energyoriented topology exploration for on-chip networks," in Proc. Des., Autom. Test Eur. Conf., Mar. 2005, pp. 1238-1243. (Pubitemid 44172179)
    • (2005) Proceedings -Design, Automation and Test in Europe, DATE '05 , vol.II , pp. 1238-1243
    • Wang, H.1    Peh, L.-S.2    Malik, S.3
  • 172
    • 84948976085 scopus 로고    scopus 로고
    • Orion: A power-performance simulator for interconnection networks
    • Nov.
    • H. Wang, X. Zhu, L. Peh, and S. Malik, "Orion: A power-performance simulator for interconnection networks," in Proc. Int. Symp. Microarchitecture, Nov. 2002, pp. 294-305.
    • (2002) Proc. Int. Symp. Microarchitecture , pp. 294-305
    • Wang, H.1    Zhu, X.2    Peh, L.3    Malik, S.4
  • 173
    • 84947211640 scopus 로고    scopus 로고
    • SoCBus: Switched network on chip for hard real time embedded systems
    • Apr.
    • D. Wiklund and D. Liu, "SoCBus: Switched network on chip for hard real time embedded systems," in Proc. Int. Parallel Distrib. Process. Symp., Apr. 2003, p. 78.1.
    • (2003) Proc. Int. Parallel Distrib. Process. Symp. , pp. 781
    • Wiklund, D.1    Liu, D.2
  • 176
    • 32544441155 scopus 로고    scopus 로고
    • Allocation and scheduling of conditional task graph in hardware/software co-synthesis
    • Mar.
    • Y. Xie and W. Wolf, "Allocation and scheduling of conditional task graph in hardware/software co-synthesis," in Proc. Des., Autom. Test Eur. Conf., Mar. 2001, pp. 620-625.
    • (2001) Proc. Des., Autom. Test Eur. Conf. , pp. 620-625
    • Xie, Y.1    Wolf, W.2
  • 177
    • 62349140799 scopus 로고    scopus 로고
    • Design of application-specific 3D networks-on-chip architectures
    • Lake Tahoe, CA, Oct. 12-15
    • S. Yan and B. Lin, "Design of application-specific 3D networks-on-chip architectures," in Proc 26th Int. Conf. Comput. Des., Lake Tahoe, CA, Oct. 12-15, 2008, pp. 142-149.
    • (2008) Proc 26th Int. Conf. Comput. Des. , pp. 142-149
    • Yan, S.1    Lin, B.2
  • 178
    • 0036053347 scopus 로고    scopus 로고
    • Analysis of power consumption on switch fabrics in network routers
    • Jun.
    • T. T. Ye, L. Benini, and G. De Micheli, "Analysis of power consumption on switch fabrics in network routers," in Proc. Des. Autom. Conf., Jun. 2002, pp. 524-529.
    • (2002) Proc. Des. Autom. Conf. , pp. 524-529
    • Ye, T.T.1    Benini, L.2    De Micheli, G.3
  • 180
    • 35348901308 scopus 로고    scopus 로고
    • Implementing tile-based chip multiprocessors with GALS clocking styles
    • Oct.
    • Z. Yu and B. Baas, "Implementing tile-based chip multiprocessors with GALS clocking styles," in Proc. Int. Conf. Comput. Des., Oct. 2006, pp. 174-179.
    • (2006) Proc. Int. Conf. Comput. Des. , pp. 174-179
    • Yu, Z.1    Baas, B.2
  • 181
    • 49249107753 scopus 로고    scopus 로고
    • SD-MAC: Design and synthesis of a hardwareefficient collision-free QoS-aware MAC protocol for wireless networkon-chip
    • Sep.
    • D. Zhao and Y. Wang, "SD-MAC: Design and synthesis of a hardwareefficient collision-free QoS-aware MAC protocol for wireless networkon-chip," IEEE Trans. Comput., vol. 57, no. 9, pp. 1230-1245, Sep. 2008.
    • (2008) IEEE Trans. Comput. , vol.57 , Issue.9 , pp. 1230-1245
    • Zhao, D.1    Wang, Y.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.