Modeling process variability in scaled CMOS technology

IEEE Design and Test of Computers

Volumn 27, Issue 2, 2010, Pages 8-16

  Saha, Samar K ^a  

^a UNIVERSITY OF COLORADO   (United States)

Author keywords

Compact variability modeling; Design and test; Gate oxide thickness variability; High k dielectric; Line edge roughness; Metal gate; Polysilicon granularity; Process variability; Random discrete dopants; Scaled CMOS technology; Statistical compact modeling

Indexed keywords

COMPACT MODELING; COMPACT VARIABILITY MODELING; GATE OXIDE; HIGH-K DIELECTRIC; LINE EDGE ROUGHNESS; METAL GATE; PROCESS VARIABILITY; SCALED CMOS; VARIABILITY MODELING;

DESIGN; ELECTRIC NETWORK ANALYSIS; POLYSILICON; POWDERS;

CMOS INTEGRATED CIRCUITS;

EID: 77950176472     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2010.50     Document Type: Article

References (12)

1. S. Saha, ''Scaling Considerations for High Performance 25 nm Metal-Oxide-Semiconductor Field Effect Transistors,'' J. Vacuum Science & Technology B: Microelectronics and Nanometer Structures, vol.19, no.6, 2001, pp. 2240-2246
2. S. Saha, ''Design Considerations for 25 nm MOSFET Devices,'' Solid-State Electronics, vol.45, no.10, 2001, pp. 1851-1857
3. K. Bernstein et al.., ''High-Performance CMOS Variability in the 65-nm Regime and Beyond,'' IBM J. Research and Development, vol.50, nos. 4-5, 2006, pp. 433-449
4. K. Kuhn et al.., ''Managing Process Variation in Intel's 45 nm CMOS Technology,'' Intel Technology J., vol.12, no.2, 2008, pp. 92-110
5. C.H. Diaz et al.., ''An Experimentally Validated Analytical Model for Gate Line-Edge Roughness (LER) Effects on Technology Scaling,'' IEEE Electron Device Letters, vol.22, no.6, 2001, pp. 287-289
6. A. Asenov et al.., ''Origin of the Asymmetry in the Magnitude of the Statistical Variability of n- and p-Channel Poly-Si Gate Bulk MOSFETs,'' IEEE Electron Device Letters, vol.29, no.8, 2008, pp. 913-915
7. A. Asenov, S. Kaya, and J.H. Davies, ''Intrinsic Threshold Voltage Fluctuations in Decanano MOSFETs Due to Local Oxide Thickness Variations,'' IEEE Trans. Electron Devices, vol.49, no.1, 2002, pp. 112-119
8. P.A. Stolk, F.P. Widdershoven, and D.B.M. Klaassen, ''Modeling Statistical Dopant Fluctuations in MOS Transistors,'' IEEE Trans. Electron Devices, vol.45, no.9, 1998, pp. 1960-1971
9. S.K. Springer et al.., ''Modeling of Variation in Submicrometer CMOS ULS Technologies,'' IEEE Trans. Electron Devices, vol.53, no.9, 2006, pp. 2168-2178
10. G. Rappitsch et al.., ''SPICE Modeling of Process Variation Using Location Depth Corner Models,'' IEEE Trans. Semiconductor Manufacturing, vol.17, no.2, 2004, pp. 201-213
11. I. Stevanovic and C.C. McAndrew, ''Quadratic Backward Propagation of Variance for Nonlinear Statistical Circuit Modeling,'' IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, vol.28, no.9, 2009, pp. 1428-1432
12. S.K. Saha, ''Managing Technology CAD for Competitive Advantage: An Efficient Approach for Integrated Circuit Fabrication Technology Development,'' IEEE Trans. Eng. Management, vol.46, no.2, 1999, pp. 221-229