DyNoC: A dynamic infrastructure for communication in dynamically reconfigurable devices

Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL

Volumn 2005, Issue , 2005, Pages 153-158

  Bobda, Christophe ^a   Ahmadinia, Ali ^a   Majer, Mateusz ^a   Teich, Jürgen ^a   Fekete, Sándor ^b   Van Der Veen, Jan ^b  

^a UNIVERSITY OF ERLANGEN NUREMBERG   (Germany)

^b TECHNICAL UNIVERSITY OF BRAUNSCHWEIG   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

COMMUNICATION SYSTEMS; COMPUTER SOFTWARE; COMPUTER SYSTEM RECOVERY; FIELD PROGRAMMABLE GATE ARRAYS; FORMAL LOGIC;

DEADLOCKS; DYNAMIC INFRASTRUCTURE; NETWORK ON CHIP (NOC); RECONFIGURABLE DEVICES;

COMPUTER NETWORKS;

EID: 33746922011     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/FPL.2005.1515715     Document Type: Conference Paper

References (6)

1. A. Ahmadinia, C. Bobda, S. Fekete, J. Teich, and J. van der Veen, "Optimal routing-conscious dynamic placement for reconfigurable devices," in Proceedings of International Conference on Field-Programmable Logic and Applications (FPL), ser. Lecture Notes in Computer Science (LNCS), vol. 3203. Antwerp, Belgium: Springer, Aug. 2004, pp. 847-851.
2. T. Marescaux, J.-Y. Mignolet, A. Bartic, W. Moffat, D. Verkest, S. Vernalde, and R. Lauwereins, "Networks on Chip as Hardware Components of an OS for Reconfigurable Systems," in Proceedings of 13th International Conference on Field Programmable Logic and Applications, Lisbon, Portugal, Sept. 2003.
3. C. Bobda, M. Majer, D. Koch, A. Ahmadinia, and J. Teich, "A dynamic noc approach for communication in reconfigurable devices," in Proceedings of International Conference on Field-Programmable Logic and Applications (FPL), ser. Lecture Notes in Computer Science (LNCS), vol. 3203. Antwerp, Belgium: Springer, Aug. 2004, pp. 1032-1036.
4. J. A. Boyan and M. L. Littman, "Packet routing in dynamically changing networks: A reinforcement learning approach," in Advances in Neural Information Processing Systems, J. D. Cowan, G. Tesauro, and J. Alspector, Eds., vol. 6. Morgan Kaufmann Publishers, Inc., 1994, pp. 671-678. [Online]. Available: citeseer.ist.psu.edu/boyan94packet.html
5. L. Benini and G. Micheli, "Network on chips: A new soc paradigm," IEEE Computer, January 2001.
6. A. Hemani, A. Jantsch, S. Kumar, A. Postula, J. Oberg, M. Millberg, and D. Lindqvist, "Network on Chip: An Architecture for Billion Transistor Era," in Proceedings of the International NorChip Conference, Sept. 2000.