Region-based routing: A mechanism to support efficient routing algorithms in NoCs

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 17, Issue 3, 2009, Pages 356-369

  Mejia, Andres ^a   Palesi, Maurizio ^b   Flich, José ^a   Kumar, Shashi ^c   Lopez, Pedro ^a   Holsmark, Rickard ^c   Duato, José ^a  

^a UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

^b UNIVERSITY OF CATANIA   (Italy)

^c JÖNKÖPING UNIVERSITY   (Sweden)

Author keywords

Application specific routing; Deadlock free routing; Networks on chip (NoC); Region based router (RBR); Router architecture; Routing algorithms; Table based router

Indexed keywords

ADAPTIVE ALGORITHMS; APPLICATIONS; BIOLOGICAL MATERIALS; DEGRADATION; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER UTILIZATION; FAULT TOLERANCE; QUALITY ASSURANCE; ROUTERS;

APPLICATION-SPECIFIC ROUTING; DEADLOCK-FREE ROUTING; NETWORKS-ON-CHIP (NOC); REGION-BASED ROUTER (RBR); ROUTER ARCHITECTURE; TABLE-BASED ROUTER;

ROUTING ALGORITHMS;

EID: 63149136484     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2008.2012010     Document Type: Article

References (37)

1. P. Guerrier and A. Greiner, "A generic architecture for on-chip packet-switched interconnections," in Proc. Conf. Des., Autom. Test Eur. (DATE), NY, 2000, pp. 250-256.
2. S. Kumar, A. Jantsch, M. Millberg, J. Oberg, J.-P. Soininen, M. Forsell, K. Tiensyrja, and A. Hemani, "A network on chip architecture and design methodology," in Proc. ISVLSI, 2002, p. 0117.
3. J. Balfour and W. J. Dally, "Design tradeoffs for tiled cmp on-chip networks," in Proc. 20th Ann. Int. Conf. Supercomput. (ICS), NY, 2006, pp. 187-198.
4. E. Bolotin, A. Morgenshtein, I. Cidon, R. Ginosar, and A. Kolodny, "Automatic hardware-efficient soc integration by qos network on chip," in Proc Electron, Circuits Syst. (ICECS), 2004, pp. 479-482 [Online]. Available: citeseer.ist.psu.edu/dally01route.html
5. E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, "Qnoc: Qos architecture and design process for network on chip," J. Syst. Arch., vol. 50, no. 2-3, pp. 105-128, 2004.
6. T. Bengtsson, S. Kumar, R. Ubar, and A. Jutman, "Off-line testing of crosstalk induced glitch faults in noc interconnects," in Proc. 24th Norchip Conf., Linkoping, Sweden, 2006, pp. 221-225.
7. W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks. San Mateo, CA: Morgan Kaufman, 2004.
8. M. Palesi, S. Kumar, and R. Holsmark, "A method for router table compression for application specific routing in mesh topology NoC architectures," in Proc. SAMOS, 2006, pp. 373-384.
9. J. Flich, A. Mejia, P. Lopez, and J. Duato, "Region-based routing. An efficient routing mechanism to tackle unreliable hardware in network on chips," presented at the 1st Int. Symp. Netw.-on-Chips, Princeton, NJ, May 2007.
10. E. Bolotin, I. Cidon, R. Ginosar, and A. Kolodny, "Routing table minimization for irregular mesh NoCs," in Proc. Conf. Des., Autom. Test Eur. (DATE), NY, 2007, pp. 942-947.
11. A. Mejia, J. Flich, J. Duato, S. Reinemo, and T. Skeie, "Segment-based routing: An efficient fault-tolerant routing algorithm for meshes and tori," presented at the 20th Int. Parallel Distrib. Process. Symp. (IPDPS), Rhodos, Grece, Apr. 2006.
12. M. Palesi, R. Holsmark, S. Kumar, and V. Catania, "A methodology for design of application specific deadlock-free routing algorithms for NoC systems," in Proc. 4th Int. Conf. Hardw./Softw. Codes. Syst. Synth. (CODES+ISSS), NY, 2006, pp. 142-147.
13. C. J. Glass and L. M. Ni, "The turn model for adaptive routing," J. ACM, vol. 41, no. 5, pp. 874-902, 1994.
14. G.-M. Chiu, "The odd-even turn model for adaptive routing," IEEE Trans. Parallel Distrib. Syst., vol. 11, no. 7, pp. 729-738, Jul. 2000.
15. T. Skeie, O. Lysne, and I. Theiss, "Layered shortest path (lash) routing in irregular system area networks," in Proc. Commun. Arch. Clusters, 2002, pp. 162-169.
16. J. Flich, P. Lopez, J. Sancho, A. Robles, and J. Duato, "Improving infiniband routing through multiple virtual networks," in Proc. 4th Int. Symp. High Perform. Comput. (ISHPC), London, U.K., 2002, pp. 49-63.
17. O. Lysne and T. Skeie, "Load balancing of irregular system area networks through multiple roots," in Proc. Int. Conf. Commun. Comput., Jun. 2001, pp. 165-171.
18. T. Skeie, O. Lysne, J. Flich, P. Lopez, A. Robles, and J. Duato, "Lashtor: A generic transition-oriented routing algorithm," in Proc. IEEE Int. Conf. Parallel Distrib. Syst. (ICPADS), 2004, pp. 595-604.
19. M. Koibuchi, A. Jouraku, K. Watanabe, and H. Amano, "Descending layers routing: A deadlock-free deterministic routing using virtual channels in system area networks with irregular topologies," in Proc. Int. Conf. Parallel Process. (ICPP), Oct. 2003, pp. 527-536.
20. L. Cherkasova, V. Kotov, and T. Rokicki, "Designing fibre channel fabrics," in Proc. Int. Conf. Comput. Des. (ICCD), Washington, DC, 1995, p. 346.
21. J. C. Sancho, A. Robles, and J. Duato, "New methodology to compute deadlock-free routing tables for irregular networks," in Proc. Workshop Commun., Arch., Appl. Netw.-Based Parallel Comput. (CANPC), Jan. 2000, pp. 45-60.
22. M. D. Schroeder, A. D. Birrell, M. Burrows, H. Murray, R. M. Needham, and T. L. Rodeheffer, "Autonet: A high-speed, self-configuring local area network using point-to-point links," IEEE J. Sel. Areas Commun., vol. 9, no. 8, pp. 1318-1335, Oct. 1991.
23. J. Sancho, A. Robles, and J. Duato, "A flexible routing scheme for networks of workstations," in Proc. 3rd Int. Symp. High Perform. Comput. (ISHPC), London, U.K., 2000, pp. 260-267.
24. M. Koibuchi, A. Funahashi, A. Jouraku, and H. Amano, "L-turn routing: An adaptive routing in irregular networks," in Proc. Int. Conf. Parallel Process. (ICPP), Washington, DC, 2001, pp. 383-392.
25. G. Ascia, V. Catania, and M. Palesi, "A multi-objective genetic approach for system-level exploration in parameterized systems-on-a-chip," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 24, no. 4, pp. 635-645, Apr. 2005.
26. L. Benini, A. Macii, E. Macii, M. Poncino, and R. Scarsi, "Architectures and synthesis algorithms for power-efficient bus interfaces," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 19, no. 9, pp. 969-980, Sep. 2000.
27. W. J. Dally and C. L. Seitz, "Deadlock-free message routing in multiprocessor interconnection networks," IEEE Trans. Comput., vol. C-36, no. 5, pp. 547-553, May 1987.
28. J. Hu and R. Marculescu, "Energy- and performance-aware mapping for regular NoC architectures," IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst., vol. 24, no. 4, pp. 551-562, Apr. 2005.
29. S.-R. Yoon, J. Lee, and S.-C. Park, "Case study: NoC based next-generation wlan receiver design in transaction level," in Proc. Int. Conf. Adv. Commun. Technol., Feb. 2006, vol. 2, pp. 1125-1128.
30. K. Srinivasan and K. S. Chatha, "A technique for low energy mapping and routing in network-on-chip architectures," in Proc. Int. Symp. Low Power Electron. Des., San Diego, CA, 2005, pp. 387-392.
31. G. Ascia, V. Catania, and M. Palesi, "Multi-objective mapping for mesh-based NoC architectures," in Proc. 2nd IEEE/ACM/IFIP Int. Conf. Hardw./Softw. Codes. Syst. Synth., Stockholm, Sweden, Sep. 2004, pp. 182-187.
32. Sourceforge.net, "Noxim: Network-on-chip simulator," 2008. [Online]. Available: http://noxim.sourceforge.net
33. G. Varatkar and R. Marculescu, "Traffic analysis for on-chip networks design of multimedia applications," in Proc. ACM/IEEE Des. Autom. Conf., Jun. 2002, pp. 510-517.
34. P. P. Pande, C. Grecu, M. Jones, A. Ivanov, and R. Saleh, "Performance evaluation and design trade-offs for network-on-chip interconnect architectures," IEEE Trans. Comput., vol. 54, no. 8, pp. 1025-1040, Aug. 2005.
35. T. T. Ye, L. Benini, and G. D. Micheli, "Packetization and routing analysis of on-chip multiprocessor networks," J. Syst. Arch., vol. 50, no. 2-3, pp. 81-104, 2004.
36. G. Ascia, V. Catania, M. Palesi, and D. Patti, "Neighbors-on-path: A new selection strategy for on-chip networks," in Proc. IEEE/ACM/IFIP Workshop Embed. Syst. Real Time Multimedia, Seoul, Korea, 2006, pp. 79-84.
37. A. S. Vaidya, A. Sivasubramaniam, and C. R. Das, "Lapses: A recipe for high performance adaptive router design," in Proc. HPCA, 1999, p. 236.