Fault modeling and simulation for crosstalk in system-on-chip interconnects

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 297-303

  Cuviello, Michael ^a   Dey, Sujit ^a   Bai, Xiaoliang ^a   Zhao, Yi ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; CROSSTALK; ERRORS; FREQUENCIES; MATHEMATICAL MODELS; MICROPROCESSOR CHIPS; THRESHOLD VOLTAGE;

DEEP SUBMICRON TECHNOLOGIES; FAULT MODELING; MAXIMAL AGGRESSOR FAULT MODELS; SOFTWARE PACKAGE SPICE; SYSTEM ON CHIP INTERCONNECTS;

INTERCONNECTION NETWORKS;

EID: 0033353059     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (16)