Enabling system-level modeling of variation-induced faults in networks-on-chips

Proceedings - Design Automation Conference

Volumn , Issue , 2011, Pages 930-935

  Aisopos, Konstantinos ^a,b   Chen, Chia Hsin Owen ^b   Peh, Li Shiuan ^b  

^a PRINCETON UNIVERSITY   (United States)

^b MASSACHUSETTS INSTITUTE OF TECHNOLOGY   (United States)

Author keywords

fault modeling; Networks on Chips; variation

Indexed keywords

COMPUTER AIDED DESIGN; ROUTERS;

CIRCUIT LEVELS; FAULT MODEL; NETWORKS ON CHIPS; PROCESS VARIATION; RANDOM FAULTS; ROUTER DESIGN; SYSTEM-LEVEL MODELING; VARIATION;

NETWORK-ON-CHIP;

EID: 80052683453     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2024724.2024931     Document Type: Conference Paper

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