Analysis of Forward Error Correction Methods for Nanoscale Networks-On-Chip

Nano-Net 2007 - Proceedings of the 2nd International Conference on Nano-Networks

Volumn , Issue , 2007, Pages

  Lehtonen, Teijo ^a   Liljeberg, Pasi ^b   Plosila, Juha ^c  

^a TURKU CENTRE FOR COMPUTER SCIENCE   (Finland)

^b UNIVERSITY OF TURKU   (Finland)

^c ACADEMY OF FINLAND   (Finland)

Author keywords

Fault tolerance; Forward error correction; Nanoscale circuits; On chip communication

Indexed keywords

FORWARD ERROR CORRECTION; NANOTECHNOLOGY; NETWORK-ON-CHIP; TIMING CIRCUITS;

CMOS-CIRCUITS; CORRECTION METHOD; FORWARD ERROR-CORRECTION; LINE-WIDTH; NANOSCALE CIRCUITS; NANOSCALE CMOS; NANOSCALE NETWORKS; NANOSCALE TECHNOLOGIES; NETWORKS ON CHIPS; ON CHIP COMMUNICATION;

FAULT TOLERANCE;

EID: 85134469001     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.4108/ICST.NANONET2007.2035     Document Type: Conference Paper

References (9)

1. International technology roadmap for semiconductors 2005. http://public.itrs.net.
2. D. Bertozzi, L. Benini, and G. D. Micheli. Error control schemes for on-chip communication links: The energy-reliability tradeoff. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(6):818–831, June 2005.
3. R. E. Blahut. Algebraic Codes for Data Transmission. Cambridge University Press, 2003.
4. C. Constantinescu. Trends and challenges in vlsi circuit reliability. IEEE Micro, 23(4):14–19, 2002.
5. M. Lajolo, M. Reorda, and M. Violante. Early evaluation of bus interconnects dependability for system-on-chip designs. In International Conference on VLSI Design, pages 371–376, 2001.
6. H. Mahmoodi, S. Mukhopadhyay, and K. Roy. Estimation of delay variations due to random-dopant fluctuations in nanoscale cmos circuits. IEEE Journal of Solid-State Circuits, 40(9).
7. S. Murali et al. Analysis of error recovery schemes for networks on chips. IEEE Design & Test of Computers, 22(5):434–442, Sep.-Oct. 2005.
8. S. Sridhara and N. Shanbhag. Coding for system-on-chip networks: A unified framework. IEEE Transactions on VLSI Systems, 13(6), June 2005.
9. H. Zimmer and A. Jantch. A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip. In IEEE/ACM/IFIP Int. Conf. on Hardware/Software Codesign and System Synthesis, pages 188–193, Oct. 2003.