A reconfigurable fault-tolerant deflection routing algorithm based on reinforcement learning for network-on-chip

3rd International Workshop on Network on Chip Architectures, NoCArc 2010, in Conjunction with the 43rd Annual IEEE/ACM International Symposium on Microarchitecture, MICRO-43

Volumn , Issue , 2010, Pages 11-16

  Feng, Chaochao ^a,b   Lu, Zhonghai ^b   Jantsch, Axel ^b   Li, Jinwen ^a   Zhang, Minxuan ^a  

^a NATIONAL UNIVERSITY OF DEFENSE TECHNOLOGY   (China)

^b ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

deflection routing; fault tolerant; NoC; reinforcement learning

Indexed keywords

AREA REDUCTION; DEFLECTION ROUTINGS; FAULT REGION; FAULT-TOLERANT; FAULT-TOLERANT ROUTING ALGORITHM; NETWORK ON CHIP; NOC; Q-LEARNING; RE-CONFIGURABLE; ROUTING TABLE; TURN MODEL;

DEFLECTION (STRUCTURES); LEARNING ALGORITHMS; REINFORCEMENT LEARNING; ROUTERS; ROUTING ALGORITHMS; TELECOMMUNICATION NETWORKS; VLSI CIRCUITS;

NETWORK ARCHITECTURE;

EID: 79951646406     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1921249.1921254     Document Type: Conference Paper

References (17)

1. C. Constantinescu, "Trends and challenges in VLSI circuit reliability," IEEE Micro, 23(4):14-19, July-August 2003.
2. Z. Lu, M. Zhong and A. Jantsch, "Evaluation of on-chip networks using deflection routing," In Proceedings of ACM Great Lakes Symposium on VLSI, pages 296-301, May 2006.
3. T. Moscibroda and O. Mutlu, "A case for bufferless routing in on-chip networks," In Proceedings of International Symposium on Computer Architecture, pages 196-207, June 2009.
4. M. Hayenga, N.E. Jerger and M. Lipasti, "SCARAB: a single cycle adaptive routing and bufferless network," In Proceedings of International Symposium on Microarchitecture, pages 244-254, June 2009.
5. A. Kohler and M. Radetzki, "Fault-tolerant architecture and deflection routing for degradable NoC switches," In Proceedings of IEEE International Symposium on Networks-on-Chip, pages 22-31, May 2009.
6. C. Feng, Z. Lu, A. Jantsch, J. Li and M. Zhang, "FoN: Fault-on-Neighbor aware routing algorithm for Networks-on-Chip," In Proceedings of the 23rd IEEE International SoC Conference, pages 441-446, September 2010.
7. D. Fick, A. Deorio, G. Chen, V. Bertacco, D. Sylvester and D. Blaauw, "A highly resilient routing algorithm for fault-tolerant NoCs," In Proceedings of Design, Automation and Test in Europe Conference and Exhibition, pages 21-26, April 2009.
8. J. Wu, "Fault-tolerant adaptive and minimal routing in mesh-connected multicomputers using extended safety levels," IEEE Transactions on Parallel and Distributed Systems, 11(2):149-159, February 2000. (Pubitemid 30583154)
9. Y.J. Suh, B.V. Dao, J. Duato and S. Yalamanchili, "Software-based rerouting for fault-tolerant pipelined communication," IEEE Transactions on Parallel and Distributed Systems, 11(3):193-211, March 2000.
10. Z. Zhang, A. Greiner and S. Taktak, "A reconfigurable routing algorithm for a fault-tolerant 2D-mesh Network-on-Chip," In Proceedings of ACM/IEEE Design Automation Conference, pages 441-446, June 2008.
11. R. Holsmark, M. Palesi and S. Kumar, "Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions," Journal of Systems Architecture, 54(3):427-440, March 2007. (Pubitemid 351615324)
12. V. Puente, J.A. Gregorio, F. Vallejo and R. Beivide, "Immunet: dependable routing for interconnection networks with arbitrary topology," IEEE Transactions on Computers, 57(12):1676-1689, December 2009.
13. A. Mejia, M. Palesi, J. Flich, S. Kumar, P. Lopez, R. Holsmark and J. Duato, "Region-based routing: a mechanism to support efficient routing algorithms in NoCs," IEEE Transactions on VLSI Systems, 17(3):356-369, May 2009.
14. M. Majer, C. Bobda, A. Ahmadinia and J. Teich, "Packet routing in dynamically changing networks on chip," In Proceedings of IEEE International Parallel and Distributed Processing Symposium, pages 154b, April 2005.
15. E. Nilsson, M. Millberg, J. Oberg and A. Jantsch, "Load distribution with the proximity congestion awareness in a network on chip," In Proceedings of Design, Automation and Test in Europe Conference and Exhibition, pages 1126-1127, March 2003.
16. X. Chen, Z. Lu, A. Jantsch and S. Chen, "Supporting distributed shared memory on multi-core network-on-chips using a dual microcoded controller," In Proceedings of Design, Automation and Test in Europe Conference and Exhibition, pages 39-44, March 2010.
17. J.A. Boyan and M.L. Littman, "Packet routing in dynamically changing networks: a reinforcement learning approach," Advances in Neural Information Processing Systems, Vol. 6, pages 671-678, 1994.