-
1
-
-
84893711333
-
A tool for automatic generation of self-checking multipliers based on residue arithmetic codes
-
[ALZ99] March Munich, Germany
-
[ALZ99] I Alzaher-Noufal, M. Nicolaidis "A Tool for Automatic Generation of Self-Checking Multipliers Based on Residue Arithmetic Codes", 1999 DATE Conference, March 1999, Munich, Germany.
-
(1999)
1999 DATE Conference
-
-
Alzaher-Noufal, I.1
Nicolaidis, M.2
-
2
-
-
0015631041
-
Arithmetic algorithms for error-coded operands
-
[AVI 73] June
-
[AVI 73] AVIZIENIS A., "Arithmetic Algorithms for Error-Coded Operands" IEEE Trans. on Comput., Vol. C-22, No. 6, pp.567-572, June 1973.
-
(1973)
IEEE Trans. on Comput.
, vol.C-22
, Issue.6
, pp. 567-572
-
-
Avizienis, A.1
-
3
-
-
0031373956
-
Attenuation of single event induced pulses in CMOS combinational logic
-
[BAZ97] December
-
[BAZ97] M. BAZE, S. BUCHNER, "Attenuation of Single Event Induced Pulses in CMOS Combinational Logic" IEEE Trans. on Nuclear Science, Vol. 44, No 6, December 1997.
-
(1997)
IEEE Trans. on Nuclear Science
, vol.44
, Issue.6
-
-
Baze, M.1
Buchner, S.2
-
4
-
-
0020102009
-
A regular layout for parallel adders
-
[BRE 82] March
-
[BRE 82] R. Brent and H. Kung, "A regular layout for parallel adders", IEEE Transactions on Computers, vol. C-31, n 3, pp. 260-264, March 1982.
-
(1982)
IEEE Transactions on Computers
, vol.C-31
, Issue.3
, pp. 260-264
-
-
Brent, R.1
Kung, H.2
-
5
-
-
84893648988
-
A fast and accurate gate-level transient fault simulation environment
-
[CHA 93] June
-
[CHA 93] H. CHA et al, "A Fast and Accurate Gate-level Transient Fault Simulation Environment", Proceedings of FTCS, June 1993
-
(1993)
Proceedings of FTCS
-
-
Cha, H.1
-
6
-
-
0028757145
-
On-line delay testing of digital circuits
-
[FRA 94] Cherry Hill, N.J., April
-
[FRA 94] Franco P., McCluskey E. J., "On-Line Delay Testing of Digital Circuits", 12th IEEE VLSI Test Symposium, Cherry Hill, N.J., April 1994.
-
(1994)
12th IEEE VLSI Test Symposium
-
-
Franco, P.1
McCluskey, E.J.2
-
7
-
-
0003495201
-
-
[HWA 79] Jhon Wiley and Sons, New York
-
[HWA 79] K. Hwang, Computer Arithmetic, Principles, Architectures and Design, Jhon Wiley and Sons, New York, 1979
-
(1979)
Computer Arithmetic, Principles, Architectures and Design
-
-
Hwang, K.1
-
9
-
-
0015651305
-
A Parallel algorithm for efficient solution of a general class of recurrence equations
-
[KOG 73] August
-
[KOG 73] P.M. Kogge and H. Stone, "A Parallel algorithm for efficient solution of a general class of recurrence equations", IEEE Transactions on Computers, vol. C-22, n 8, pp. 786-792, August 1973
-
(1973)
IEEE Transactions on Computers
, vol.C-22
, Issue.8
, pp. 786-792
-
-
Kogge, P.M.1
Stone, H.2
-
10
-
-
0008519958
-
-
[MET 98] ITC October Washington, DC
-
[MET 98] C. Metra, M. Favalli, B. Ricco, "On-Line Detection of Logic Errors due to Crosstalk, Delay, and Transient Faults", ITC October 18-23, 1998, Washington, DC.
-
(1998)
On-Line Detection of Logic Errors Due to Crosstalk, Delay, and Transient Faults
, pp. 18-23
-
-
Metra, C.1
Favalli, M.2
Ricco, B.3
-
12
-
-
0001749167
-
On checking an Adder
-
[PET 58] April
-
[PET 58] PETERSON W.W. "On checking an Adder", IBM J. Res. Develop. 2, pp.166-168, April 1958
-
(1958)
IBM J. Res. Develop
, Issue.2
, pp. 166-168
-
-
Peterson, W.W.1
-
13
-
-
0003525992
-
-
[PET 72] second Ed., The MIT press, Cambridge, Massachusetts
-
[PET 72] PETERSON W.W., WELDON E.J., "Error-Correcting Codes", second Ed., The MIT press, Cambridge, Massachusetts, 1972
-
(1972)
Error-Correcting Codes
-
-
Peterson, W.W.1
Weldon, E.J.2
-
14
-
-
84913396280
-
Conditional-sum addition logic
-
[SKL 60] June
-
[SKL 60] J. Sklanski, "Conditional-sum addition logic", IRE Transaction on Electronic Computers, vol. EC-9, n 2, pp. 226-231, June 1960.
-
(1960)
IRE Transaction on Electronic Computers
, vol.EC-9
, Issue.2
, pp. 226-231
-
-
Sklanski, J.1
|