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Volumn , Issue , 2000, Pages 591-598

Cost reduction and evaluation of a temporary faults detecting technique

Author keywords

[No Author keywords available]

Indexed keywords

ARITHMETIC CIRCUIT; CHANNEL WIDTHS; DETECTING TECHNIQUE; FAULT TOLERANT TECHNIQUE; PERFORMANCE COSTS; TEMPORARY FAULT; TIME REDUNDANCY; TIMING ERRORS;

EID: 33847113086     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2000.840845     Document Type: Conference Paper
Times cited : (154)

References (15)
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    • Alzaher-Noufal, I.1    Nicolaidis, M.2
  • 2
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    • Attenuation of single event induced pulses in CMOS combinational logic
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    • Baze, M.1    Buchner, S.2
  • 4
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    • A regular layout for parallel adders
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    • Brent, R.1    Kung, H.2
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    • Cha, H.1
  • 6
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    • On-line delay testing of digital circuits
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    • (1994) 12th IEEE VLSI Test Symposium
    • Franco, P.1    McCluskey, E.J.2
  • 9
    • 0015651305 scopus 로고
    • A Parallel algorithm for efficient solution of a general class of recurrence equations
    • [KOG 73] August
    • [KOG 73] P.M. Kogge and H. Stone, "A Parallel algorithm for efficient solution of a general class of recurrence equations", IEEE Transactions on Computers, vol. C-22, n 8, pp. 786-792, August 1973
    • (1973) IEEE Transactions on Computers , vol.C-22 , Issue.8 , pp. 786-792
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  • 12
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    • On checking an Adder
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.