Dual-layer adaptive error control for network-on-chip links

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 20, Issue 7, 2012, Pages 1304-1317

  Yu, Qiaoyan ^a   Ampadu, Paul ^b  

^a UNIVERSITY OF NEW HAMPSHIRE   (United States)

^b University of Rochester   (United States)

Author keywords

Energy efficiency; error control coding (ECC); network on chip (NoC); on chip interconnect; product code; reliability; transient error

Indexed keywords

ERROR CONTROL CODING; NETWORK ON CHIP; ON CHIP INTERCONNECT; PRODUCT CODE; TRANSIENT ERRORS;

ENERGY EFFICIENCY; INVENTORY CONTROL; NETWORK LAYERS; RELIABILITY; VLSI CIRCUITS;

SERVERS;

EID: 84862011580     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2011.2156436     Document Type: Article

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