-
2
-
-
1542690244
-
Soft errors in advanced semiconductor devices-Part I: The three radiation sources
-
Mar.
-
R. C. Baumann, "Soft errors in advanced semiconductor devices-Part I: The three radiation sources," IEEE Trans. Device Mater. Rel., vol. 1, no. 1, pp. 17-22, Mar. 2001.
-
(2001)
IEEE Trans. Device Mater. Rel.
, vol.1
, Issue.1
, pp. 17-22
-
-
Baumann, R.C.1
-
3
-
-
0034450511
-
Impact of CMOS technology scaling on the atmospheric neutron soft error rate
-
Dec.
-
P. Hazucha and C. Svensson, "Impact of CMOS technology scaling on the atmospheric neutron soft error rate," IEEE Trans, Nucl. Sci, vol. 47, no. 6, pp. 2586-2594, Dec. 2000.
-
(2000)
IEEE Trans, Nucl. Sci
, vol.47
, Issue.6
, pp. 2586-2594
-
-
Hazucha, P.1
Svensson, C.2
-
4
-
-
0036927879
-
The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction
-
San Francisco, CA
-
R. C. Baumann, 'The impact of technology scaling on soft error rate performance and limits to the efficacy of error correction," in Proc. Dig. Int. Electron Devices Meeting, San Francisco, CA, 2002, pp. 329-332.
-
(2002)
Proc. Dig. Int. Electron Devices Meeting
, pp. 329-332
-
-
Baumann, R.C.1
-
5
-
-
0036931372
-
Modeling the effect of technology trends on the soft error rate of combinational logic
-
Washington, DC
-
P. Shivakumar et al., "Modeling the effect of technology trends on the soft error rate of combinational logic," in Proc. Int. Conf. Dependable Systems Networks, Washington, DC, 2002, pp. 389-398.
-
(2002)
Proc. Int. Conf. Dependable Systems Networks
, pp. 389-398
-
-
Shivakumar, P.1
-
6
-
-
0029770964
-
Soft-error Monte Carlo modeling program, SEMM
-
Jan.
-
P. C. Murley and G. R. Srinivasan, "Soft-error Monte Carlo modeling program, SEMM," IBM J. Res. Develop., vol. 40, no. 1, pp. 109-118, Jan. 1996.
-
(1996)
IBM J. Res. Develop.
, vol.40
, Issue.1
, pp. 109-118
-
-
Murley, P.C.1
Srinivasan, G.R.2
-
7
-
-
0026400768
-
Simulation of SEU transients in CMOS ICs
-
Dec.
-
N. Kaul, B. I. Bhuva, and S. E. Kerns, "Simulation of SEU transients in CMOS ICs," IEEE Trans. Nucl. Sci., vol. 38, no. 6, pp. 1514-1520, Dec. 1991.
-
(1991)
IEEE Trans. Nucl. Sci.
, vol.38
, Issue.6
, pp. 1514-1520
-
-
Kaul, N.1
Bhuva, B.I.2
Kerns, S.E.3
-
8
-
-
0003850954
-
-
Upper Saddle River, NJ: Prentice-Hall
-
J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits, 2nd ed. Upper Saddle River, NJ: Prentice-Hall, 2002.
-
(2002)
Digital Integrated Circuits, 2nd Ed.
-
-
Rabaey, J.M.1
Chandrakasan, A.2
Nikolic, B.3
-
9
-
-
0030286383
-
A gate-level simulation environment for alpha-particle-induced transient faults
-
Nov.
-
H. Cha, E. M. Rudnick, J. H. Patel, R. K. Iyer, and G. S. Choi, "A gate-level simulation environment for alpha-particle-induced transient faults,"IEEE Trans. Comput., vol. 45, no. 11, pp. 1248-1256, Nov. 1996.
-
(1996)
IEEE Trans. Comput.
, vol.45
, Issue.11
, pp. 1248-1256
-
-
Cha, H.1
Rudnick, E.M.2
Patel, J.H.3
Iyer, R.K.4
Choi, G.S.5
-
10
-
-
10444278059
-
Sizing CMOS circuits for increased transient error tolerance
-
Funchal, Portugal
-
Y. S. Dhillon, A. U. Diril, A. Chatterjee, and A. D. Singh, "Sizing CMOS circuits for increased transient error tolerance," in Proc. IEEE Int. On-Line Testing Symp., Funchal, Portugal, 2004, pp. 11-16.
-
(2004)
Proc. IEEE Int. On-line Testing Symp.
, pp. 11-16
-
-
Dhillon, Y.S.1
Diril, A.U.2
Chatterjee, A.3
Singh, A.D.4
-
11
-
-
33646909420
-
Soft-error tolerance analysis and optimization of nanometer circuits
-
Munich, Germany
-
Y. S. Dhillon, A. U. Diril, and A. Chatterjee, "Soft-error tolerance analysis and optimization of nanometer circuits," in Proc. Design, Automation, Test Eur., Munich, Germany, 2005, pp. 288-293.
-
(2005)
Proc. Design, Automation, Test Eur.
, pp. 288-293
-
-
Dhillon, Y.S.1
Diril, A.U.2
Chatterjee, A.3
-
12
-
-
4444372346
-
A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits
-
San Diego, CA
-
C. Zhao, X. Bai, and S. Dey, "A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits," in Proc. Design Automation Conf., San Diego, CA, 2004, pp. 894-899.
-
(2004)
Proc. Design Automation Conf.
, pp. 894-899
-
-
Zhao, C.1
Bai, X.2
Dey, S.3
-
13
-
-
0026838205
-
Simulation and analysis of transient faults in digital circuits
-
Mar.
-
F. L. Yang and R. A. Saleh, "Simulation and analysis of transient faults in digital circuits," IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 258-264, Mar. 1992.
-
(1992)
IEEE J. Solid-state Circuits
, vol.27
, Issue.3
, pp. 258-264
-
-
Yang, F.L.1
Saleh, R.A.2
-
14
-
-
0034452351
-
Analysis of single-event effects in combinational logic-Simulation of the AM2901 bitslice processor
-
Dec.
-
L. W. Massengill, A. E. Baranski, D. O. Van Nort, J. Meng, and B. L. Bhuva, "Analysis of single-event effects in combinational logic-Simulation of the AM2901 bitslice processor," IEEE Trans. Nucl. Sci., vol. 47, no. 6, pp. 2609-2615, Dec. 2000.
-
(2000)
IEEE Trans. Nucl. Sci.
, vol.47
, Issue.6
, pp. 2609-2615
-
-
Massengill, L.W.1
Baranski, A.E.2
Van Nort, D.O.3
Meng, J.4
Bhuva, B.L.5
-
15
-
-
0029490982
-
An SEU analysis approach for error propagation in digital VLSI CMOS ASICs
-
Dec.
-
M. P. Baze, S. P. Buchner, W. G. Bartholet, and T. A. Dao, "An SEU analysis approach for error propagation in digital VLSI CMOS ASICs," IEEE Trans. Nucl. Sci., vol. 42, no. 6, pp. 1863-1869, Dec. 1995.
-
(1995)
IEEE Trans. Nucl. Sci.
, vol.42
, Issue.6
, pp. 1863-1869
-
-
Baze, M.P.1
Buchner, S.P.2
Bartholet, W.G.3
Dao, T.A.4
-
16
-
-
8444229189
-
Single-event transients in fast electronic circuits
-
Vancouver, BC, Canada, Section V
-
S. P. Buchner and M. P. Baze, "Single-event transients in fast electronic circuits," in Short Course IEEE Nuclear Space Radiation Effects Conf., Vancouver, BC, Canada, 2001, pp. 1-105. Section V.
-
(2001)
Short Course IEEE Nuclear Space Radiation Effects Conf.
, pp. 1-105
-
-
Buchner, S.P.1
Baze, M.P.2
-
17
-
-
84955261303
-
A systematic approach to ser estimation and solutions
-
Dallas, TX
-
H. T. Nguyen and Y. Yagil, "A systematic approach to SER estimation and solutions," in Proc. IEEE Int. Reliability Physics Symp., Dallas, TX, 2003, pp. 60-70.
-
(2003)
Proc. IEEE Int. Reliability Physics Symp.
, pp. 60-70
-
-
Nguyen, H.T.1
Yagil, Y.2
-
18
-
-
16244391105
-
A soft error rate analysis (SERA) methodology
-
San Jose, CA
-
M. Zhang and N. R. Shanbhag, "A soft error rate analysis (SERA) methodology," in Proc. Int. Conf. Computer-Aided Design, San Jose, CA, 2004, pp. 111-118.
-
(2004)
Proc. Int. Conf. Computer-aided Design
, pp. 111-118
-
-
Zhang, M.1
Shanbhag, N.R.2
-
19
-
-
0027576605
-
Single event upsets in avionics
-
Apr.
-
A. Taber and E. Normand, "Single event upsets in avionics," IEEE Trans. Nucl. Sci., vol. 40, no. 2, pp. 120-126, Apr. 1993.
-
(1993)
IEEE Trans. Nucl. Sci.
, vol.40
, Issue.2
, pp. 120-126
-
-
Taber, A.1
Normand, E.2
-
20
-
-
0018716817
-
Effect of cosmic rays on computer memories
-
Nov.
-
J. F. Ziegler and W. A. Lanford, "Effect of cosmic rays on computer memories," Science, vol. 206, no. 4420, pp. 776-788, Nov. 1979.
-
(1979)
Science
, vol.206
, Issue.4420
, pp. 776-788
-
-
Ziegler, J.F.1
Lanford, W.A.2
-
21
-
-
0029732557
-
Terrestrial cosmic rays
-
Jan.
-
J. F. Ziegler, "Terrestrial cosmic rays," IBM J. Res. Develop., vol. 40, no. 1,pp. 19-39, Jan. 1996.
-
(1996)
IBM J. Res. Develop.
, vol.40
, Issue.1
, pp. 19-39
-
-
Ziegler, J.F.1
-
22
-
-
0029342231
-
Calculation of the soft error rate of submicron CMOS logic circuits
-
Jul.
-
T. Juhnke et al., "Calculation of the soft error rate of submicron CMOS logic circuits," IEEE J. Solid-State Circuits, vol. 30, no. 7, pp. 830-834, Jul. 1995.
-
(1995)
IEEE J. Solid-state Circuits
, vol.30
, Issue.7
, pp. 830-834
-
-
Juhnke, T.1
-
23
-
-
0034297471
-
Cosmic-ray soft error rate characterization of a starndard 0.6-μm CMOS process
-
Oct.
-
P. Hazucha and C. Svensson, "Cosmic-ray soft error rate characterization of a starndard 0.6-μm CMOS process," IEEE J. Solid-State Circuits, vol. 35, no. 10, pp. 2586-2594, Oct. 2000.
-
(2000)
IEEE J. Solid-state Circuits
, vol.35
, Issue.10
, pp. 2586-2594
-
-
Hazucha, P.1
Svensson, C.2
-
24
-
-
0029752087
-
Critical charge calculations for a bipolar SRAM array
-
Jan.
-
L. B. Freeman, "Critical charge calculations for a bipolar SRAM array,"IBM J. Res. Develop., vol. 40, no. 1, pp. 119-129, Jan. 1996.
-
(1996)
IBM J. Res. Develop.
, vol.40
, Issue.1
, pp. 119-129
-
-
Freeman, L.B.1
-
25
-
-
0141572836
-
-
Ph.D. dissertation, Dept. Physics Measurement Technol., Linköping Univ., Linköping, Sweden
-
P. Hazucha, "Background radiation and soft errors in CMOS circuits,"Ph.D. dissertation, Dept. Physics Measurement Technol., Linköping Univ., Linköping, Sweden, 2000.
-
(2000)
Background Radiation and Soft Errors in CMOS Circuits
-
-
Hazucha, P.1
-
26
-
-
70449462530
-
Analysis of soft error rate in flip-flops and scannable latches
-
Tampere, Finland
-
R. Ramanarayanan et al., "Analysis of soft error rate in flip-flops and scannable latches," in Proc. IEEE Int. SOC Conf., Tampere, Finland, 2003, pp. 231-234.
-
(2003)
Proc. IEEE Int. SOC Conf.
, pp. 231-234
-
-
Ramanarayanan, R.1
-
27
-
-
0027829860
-
A fast and accurate gate-level transient fault simulation environment
-
Toulouse, France
-
H. Cha et al., "A fast and accurate gate-level transient fault simulation environment," in Proc. Dig. Papers Int. Symp. Fault-Tolerant Computing, Toulouse, France, 1993, pp. 310-319.
-
(1993)
Proc. Dig. Papers Int. Symp. Fault-tolerant Computing
, pp. 310-319
-
-
Cha, H.1
-
28
-
-
0020298427
-
Collection of charge on junction nodes from ion tracks
-
Dec.
-
G. C. Messenger, "Collection of charge on junction nodes from ion tracks," IEEE Trans. Nucl. Sci., vol. NS-29, no. 6, pp. 2024-2031, Dec. 1982.
-
(1982)
IEEE Trans. Nucl. Sci.
, vol.NS-29
, Issue.6
, pp. 2024-2031
-
-
Messenger, G.C.1
-
29
-
-
11144230787
-
Timing vulnerability factors of sequentials
-
Sep.
-
N. Seifert and N. Tam, "Timing vulnerability factors of sequentials," IEEE Tram. Device Mater. Rel., vol. 4, no. 3, pp. 516-522, Sep. 2004.
-
(2004)
IEEE Tram. Device Mater. Rel.
, vol.4
, Issue.3
, pp. 516-522
-
-
Seifert, N.1
Tam, N.2
|