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Volumn 25, Issue 10, 2006, Pages 2140-2155

Soft-Error-Rate-Analysis (SERA) methodology

Author keywords

Combinational logic circuits; Integrated circuit reliability; Single event transient (SET); Single event upset (SEU); Soft error; Soft error rate (SER)

Indexed keywords

COMBINATIONAL LOGIC CIRCUITS; INTEGRATED-CIRCUIT RELIABILITY; SINGLE-EVENT TRANSIENT (SET); SINGLE-EVENT UPSET (SEU); SOFT ERRORS; SOFT-ERROR RATE (SER);

EID: 33748331354     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.862738     Document Type: Article
Times cited : (121)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.