Soft-Error-Rate-Analysis (SERA) methodology

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Volumn 25, Issue 10, 2006, Pages 2140-2155

  Zhang, Ming ^a,b   Shanbhag, Naresh R ^a,b  

^a IEEE   (United States)

^b University of Illinois at Urbana Champaign   (United States)

Author keywords

Combinational logic circuits; Integrated circuit reliability; Single event transient (SET); Single event upset (SEU); Soft error; Soft error rate (SER)

Indexed keywords

COMBINATIONAL LOGIC CIRCUITS; INTEGRATED-CIRCUIT RELIABILITY; SINGLE-EVENT TRANSIENT (SET); SINGLE-EVENT UPSET (SEU); SOFT ERRORS; SOFT-ERROR RATE (SER);

CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC POTENTIAL; GRAPH THEORY; INTEGRATED CIRCUITS; PROBABILITY;

ERROR DETECTION;

EID: 33748331354     PISSN: 02780070     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCAD.2005.862738     Document Type: Article

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