A dual-layer method for transient and permanent error co-management in NoC links

IEEE Transactions on Circuits and Systems II: Express Briefs

Volumn 58, Issue 1, 2011, Pages 36-40

  Yu, Qiaoyan ^a   Ampadu, Paul ^a  

^a UNIVERSITY OF ROCHESTER   (United States)

Author keywords

Error control coding (ECC); fault tolerant routing; network on chip (NoC); on chip interconnect; permanent error; reliability; spare wire; transient error

Indexed keywords

ERRORS; NETWORK ARCHITECTURE; NETWORK LAYERS; RELIABILITY; SERVERS; WIRE;

ERROR CONTROL CODING; FAULT TOLERANT ROUTING; NETWORK-ON-CHIP(NOC); ON CHIP INTERCONNECT; PERMANENT ERRORS; TRANSIENT ERRORS;

NETWORK-ON-CHIP;

EID: 79251472729     PISSN: 15497747     EISSN: 15583791     Source Type: Journal    
DOI: 10.1109/TCSII.2010.2092817     Document Type: Article

References (19)

1. J. D. Owens, W. J. Dally, R. Ho, D. N. Jayasimha, S. W. Keckler, and L. S. Peh, "Research challenges for on-chip interconnection networks", IEEE Micro, vol. 27, no. 5, pp. 96-108, Sep./Oct. 2007.
2. G. De Micheli and L. Benini, Networks on Chips. San Mateo, CA: Morgan Kaufmann, 2007.
3. S. Shamshiri and K.-T. Cheng, "Yield and cost analysis of a reliable NoC", in Proc. 27th IEEE VLSI Test Symp., May 2009, pp. 173-178.
4. D. Bertozzi, L. Benini, and G. De Micheli, "Error control scheme for onchip communication links: The energy-reliability tradeoff", IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, no. 6, pp. 818-831, Jun. 2005.
5. B. Fu and P. Ampadu, "On hamming product codes with type-II hybrid ARQ for on-chip interconnects", IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 56, no. 9, pp. 2042-2054, Sep. 2009.
6. L. Li, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, "Adaptive error protection for energy efficiency", in Proc. ICCAD, Nov. 2003, pp. 2-7.
7. Q. Yu and P. Ampadu, "Adaptive error control for nanometer scale NoC links", IET Comput. Digital Techn.-Special Issue on Advances in Nanoelectronics Circuits and Syst., vol. 3, no. 6, pp. 643-659, Nov. 2009.
8. M. Pirretti, G. M. Link, R. R. Brooks, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin, "Fault tolerant algorithms for network-on-chip interconnect", in Proc. ISVLSI, Feb. 2004, pp. 46-51.
9. M. Ali, M. Welzl, S. Hessler, and S. Hellebrand, "An efficient fault tolerant mechanism to deal with permanent and transient failures in a network on chip", Int. J. High Performance Syst. Archit., vol. 1, no. 2, pp. 113-123, Oct. 2007.
10. T. Lehtonen, P. Liljeberg, and J. Plosila, "Online reconfigurable self-timed links for fault tolerant NoC", VLSI Des., vol. 2007, pp. 1-13, Apr. 2007.
11. A. Sanusi and M. A. Bayoumi, "Smart-flooding: A novel scheme for fault-tolerant NoCs", in Proc. IEEE SOC Conf., Sep. 2009, pp. 259-262.
12. Q. Yu and P. Ampadu, "Transient and permanent error co-management for reliable network-on-chip", in Proc. NOCS, May 2010, pp. 145-154.
13. T. Lehtonen, D. Wolpert, P. Lijeberg, J. Plosila, and P. Ampadu, "Self-adaptive system for addressing permanent errors in on-chip interconnects", IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 18, no. 4, pp. 527-540, Apr. 2010.
14. E. Salminen, A. Kulmala, and T. D. Hämäläinen, Survey of Networkon-Chip Proposals, pp. 1-13, Beaverton, OR: OCP-IP, Mar. 2008, White paper.
15. J. Bahn, J. Yang, and N. Bagherzadeh, "Parallel FFT algorithms on Network-on-Chips", in Proc. ITNG, Apr. 2008, pp. 1087-1093.
16. T. Lehtonen, P. Liljeberg, and J. Plosila, "Analysis for forward error correction methods for nanoscale networks-on-chip", in Proc. Nano-Nets, Sep. 2007, pp. 1-5.
17. S. R. Sridhara and N. R. Shanbhag, "Coding for system-on-chip a networks: A unified framework", IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 6, pp. 655-667, Jun. 2005.
18. D. Rossi, C. Metra, A. K. Nieuwland, and A. Katoch, "Exploiting ECC redundancy to minimize crosstalk impact", IEEE Des. Test Comput., vol. 22, no. 1, pp. 59-70, Jan./Feb. 2005.
19. A. Ganguly, P. P. Pande, and B. Belzer, "Crosstalk-aware channel coding schemes for energy efficient and reliable NoC Interconnects", IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 17, no. 11, pp. 1626-1639, Nov. 2009.