Design of fault tolerant Network Interfaces for NoCs

Proceedings - 2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011

Volumn , Issue , 2011, Pages 393-400

  Fiorin, Leandro ^a   Micconi, Laura ^b   Sami, Mariagiovanna ^c  

^a UNIVERSITY OF LUGANO   (Switzerland)

^b TECHNICAL UNIVERSITY OF DENMARK   (Denmark)

^c POLITECNICO DI MILANO   (Italy)

Author keywords

Fault tolerance; Network Interface; Networks on Chip; Systems on Chip

Indexed keywords

AS INTERFACES; COMMUNICATION INFRASTRUCTURE; DEEP SUB-MICRON; ENERGY REDUCTION; FAULT TOLERANT SOLUTIONS; FAULT-TOLERANT NETWORKS; FUNCTIONAL FAULT MODEL; IP CORE; NETWORK INTERFACE; NETWORKS ON CHIPS; SINGLE EVENT UPSETS; SOFT ERROR; SYSTEM ON CHIPS; SYSTEMS ON CHIPS; TRIPLE MODULAR REDUNDANCY;

DESIGN; DIGITAL STORAGE; ERRORS; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; INTERFACES (COMPUTER); MICROPROCESSOR CHIPS; REDUNDANCY; SYSTEMS ANALYSIS; TELECOMMUNICATION NETWORKS;

NETWORK ARCHITECTURE;

EID: 80054974029     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSD.2011.54     Document Type: Conference Paper

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