Fault-tolerant architecture and deflection routing for degradable NoC switches

Proceedings - 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2009

Volumn , Issue , 2009, Pages 22-31

  Kohler, Adán ^a   Radetzki, Martin ^a  

^a UNIVERSITY OF STUTTGART   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

DEFLECTION ROUTINGS; FAULT-TOLERANT; FUNCTIONAL FAULT MODEL; GRACEFUL DEGRADATION; NETWORKS ON CHIPS; NOC SWITCH; ON CHIP COMMUNICATION; ON-LINE FAULT DIAGNOSIS; PACKET THROUGHPUT; STRUCTURAL REDUNDANCY;

ASYNCHRONOUS SEQUENTIAL LOGIC; BIOLOGICAL MATERIALS; ELECTRIC NETWORK TOPOLOGY; FAILURE ANALYSIS; QUALITY ASSURANCE; REDUNDANCY; ROUTING ALGORITHMS;

MICROPROCESSOR CHIPS;

EID: 70349789944     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2009.5071441     Document Type: Conference Paper

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