Time redundancy based scan flip-flop reuse to reduce ser of combinational logic

Proceedings - International Symposium on Quality Electronic Design, ISQED

Volumn , Issue , 2006, Pages 617-624

  Elakkumanan, Praveen ^a   Prasad, Kishan ^a   Sridhar, Ramalingam ^a  

^a the State University of New York   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BENCHMARK CIRCUIT; COMBINATIONAL LOGIC; FAULT TOLERANT TECHNIQUE; MITIGATION SCHEMES; SINGLE EVENT TRANSIENTS; TECHNOLOGY NODES; TECHNOLOGY SCALING; TIME REDUNDANCY;

BENCHMARKING; FLIP FLOP CIRCUITS; REDUNDANCY;

TRANSIENTS;

EID: 84886735426     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2006.137     Document Type: Conference Paper

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