A distributed and topology-agnostic approach for on-line NoC testing

NOCS 2011: The 5th ACM/IEEE International Symposium on Networks-on-Chip

Volumn , Issue , 2011, Pages 113-120

  Kakoee, Mohammad Reza ^a   Bertacco, Valeria ^b   Benini, Luca ^a  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b UNIVERSITY OF MICHIGAN   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CONTROL PATH; DATA PATHS; FAULT COVERAGES; GENERAL TOPOLOGY; HARDWARE OVERHEADS; LARGE-SCALE NETWORK; NOC TESTING; ON-LINE TESTING; ON-LINE TESTS; SIMULATION RESULT; STUCK-AT FAULTS; TEST COMPONENTS; TRIPLE MODULE REDUNDANCY;

MICROPROCESSOR CHIPS; TESTING; TOPOLOGY; WIRE;

ROUTERS;

EID: 79960335541     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1999946.1999965     Document Type: Conference Paper

References (27)

1. E. Cota, F.L. Kastensmidt, M. Cassel, M. Herve, P. Almeida, P. Meirelles, A. Amory, M. Lubaszewski, "A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip," IEEE Trans. on Computers, Vol. 57, No. 9, pp. 1202-1215, 2008.
2. M. Herve, P. Almeida, F.L Kastensmidt, E. Cota, M. Lubaszewski, "Concurrent test of Network-on-Chip interconnects and routers," Proc. IEEE LATW, pp. 1-6, 2010.
3. C. Grecu, et al., "On-line fault detection and location for NoC interconnects," Proc. IEEE IOLTS, pp. 6-11, 2006.
4. M.R. Kakoee, et al., "ReliNoC: A Reliable Network for Priority-Based On-Chip Communication," Proc. ACM/IEEE DATE, pp. 667-672, 2011.
5. S. Rodrigo, et al., "Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing," Proc. ACM/IEEE NoCS, pp. 25-32, 2010.
6. D. Fick, et al., "A highly resilient routing algorithm for fault-tolerant NoCs," Proc. ACM/IEEE DATE, pp. 21-26, 2009.
7. M.E. Gomez et al., "An efficient fault-tolerant routing methodology for meshes and tori," IEEE Computer Architecture Letters, vol. 3, No. 1, pp. 3-3, 2004.
8. C.-T. Ho, L. Stockmeyer, "A new approach to fault-tolerant wormhole routing for mesh-connected parallel computers," IEEE Trans. on Computers, Vol. 53, No. 4, pp. 427-439, 2004.
9. D. Park, et al., "Exploring fault-tolerant network-on-chip architectures," Proc. ACM/IEEE DSN, pp. 93-104, 2006.
10. Wei Song Edwards, D. Nunez-Yanez, J.L. Dasgupta, S., "Adaptive stochastic routing in fault-tolerant on-chip networks," Proc. ACM/IEEE NoCS, pp. 32-37 , 2009.
11. A. Alaghi, N. Karimi, M. Sedghi, Z. Navabi, "Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Model," Proc. IEEE DFT, pp. 21-29, 2007.
12. Young Hoon Kang, Taek-Jun Kwon, Jeffrey Draper, "Fault-Tolerant Flow Control in On-chip Networks," Proc. ACM/IEEE NoCS , pp. 79-86, 2010.
13. S. Borkar,"Microarchitecture and design challenges for gigascale integration," Proc. ACM/IEEE MICRO, keynote address, pp. 3-3, 2004.
14. S. Borkar,"Designing reliable systems from unreliable components: the challenges of transistor variability and degradation," IEEE Micro, Vol. 25, No. 6, pp. 10-16, 2005.
15. J. W. McPherson, "Reliability challenges for 45nm and beyond," Proc. ACM/IEEE DAC, pp. 176-181, 2006.
16. T. Bjerregaard, Shankar Mahadevan, "A survey of research and practices of network-on-chip," ACM Computer Survey, Vol. 38, No. 1, 2006.
17. T. Bengtsson, S. Kumar, Z. Peng, "Application Area Specific System Level Fault Models: A Case Study with a Simple NoC Switch," Proc. IDT, 2006.
18. D. Bertozzi, L. Benini, "Xpipes:Anetwork-on-chip architecture for gigascale system-on-chip," IEEE Circuits Syst. Mag., Vol. 4, No. 2, pp. 18-31, 2004.
19. F. Fazzino, et al., Noxim: Network-on-chip simulator [Online]. http://noxim.sourceforge.net
20. http://techresearch.intel.com/articles/Tera-Scale/1421.htm.
21. http://techresearch.intel.com/articles/Tera-Scale/1449.htm.
22. http://www.tilera.com/products/processors.php.
23. C. Bienia, et al., "The PARSEC benchmark suite: characterization and architectural implications," Proc. ACM PACT, pp. 72-81, 2008.
24. P.S. Magnusson, et al., "Simics: A full system simulation platform," IEEE Computer, Vol. 35, No. 2, pp. 50-58, 2002.
25. M. M. K. Martin, et al., "Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset," SIGARCH Computer Architecture News, Vol. 33, No. 4, pp. 92-99, 2005.
26. N. Agarwal, et al., "GARNET: A detailed on-chip network model inside a full-system simulator," Proc. IEEE ISPASS, pp. 33-42, 2009.
27. Plasma microprocessor description (http://www.opencores.org)