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Volumn , Issue , 2007, Pages 43-48

Configurable error control scheme for NoC signal integrity

Author keywords

[No Author keywords available]

Indexed keywords

CODES (STANDARDS); CODES (SYMBOLS); ELECTRIC NETWORK TOPOLOGY; ERROR DETECTION; QUALITY ASSURANCE; QUALITY OF SERVICE; RELIABILITY; SIGNAL PROCESSING;

EID: 46749157523     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IOLTS.2007.24     Document Type: Conference Paper
Times cited : (54)

References (13)
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  • 2
    • 0036149420 scopus 로고    scopus 로고
    • Network on Chips: A New SoC Paradigm
    • Jan
    • L. Benini, G. De Micheli, "Network on Chips: A New SoC Paradigm", IEEE Computer, Jan. 2002, pp. 70-78.
    • (2002) IEEE Computer , pp. 70-78
    • Benini, L.1    De Micheli, G.2
  • 3
    • 0032691273 scopus 로고    scopus 로고
    • Bus Crosstalk Fault-Detection Capabilities of Error Detecting Codes for On-Line Testing
    • Sept
    • M. Favalli, C. Metra, "Bus Crosstalk Fault-Detection Capabilities of Error Detecting Codes for On-Line Testing", IEEE Trans. on VLSI Systems, Sept. 1999, pp. 392-396.
    • (1999) IEEE Trans. on VLSI Systems , pp. 392-396
    • Favalli, M.1    Metra, C.2
  • 4
    • 1142287741 scopus 로고    scopus 로고
    • A Fault-Model Notation and Error-Control Scheme for Switch-to-Switch Buses in a Network-on-Chip
    • H. Zimmer, A. Jantsch, "A Fault-Model Notation and Error-Control Scheme for Switch-to-Switch Buses in a Network-on-Chip", Proc. ACM CODES+ISSS'03, 2003, pp. 188-193.
    • (2003) Proc. ACM CODES+ISSS'03 , pp. 188-193
    • Zimmer, H.1    Jantsch, A.2
  • 5
    • 2942641861 scopus 로고    scopus 로고
    • Quality-of-Service and Error Control Techniques for Network-on-Chip Architectures
    • P. Vellanki, N. Banerjee, K.S. Chatha, "Quality-of-Service and Error Control Techniques for Network-on-Chip Architectures", Proc. GLSVLSI'04, 2004, pp. 45-50.
    • (2004) Proc. GLSVLSI'04 , pp. 45-50
    • Vellanki, P.1    Banerjee, N.2    Chatha, K.S.3
  • 7
    • 33750904573 scopus 로고    scopus 로고
    • Performance Driven Reliable Link Design for Networks on Chips
    • R. R. Tamhankar, S. Murali, G. De Micheli, "Performance Driven Reliable Link Design for Networks on Chips", ASP-DAC 2005, pp. 749-754.
    • (2005) ASP-DAC , pp. 749-754
    • Tamhankar, R.R.1    Murali, S.2    De Micheli, G.3
  • 8
    • 27344448860 scopus 로고    scopus 로고
    • Analysis of Error Recovery Schemes for Networks on Chips
    • Sep.-Oct
    • S. Murali, et al., "Analysis of Error Recovery Schemes for Networks on Chips", IEEE Design &Test of Computers, Sep.-Oct. 2005, pp. 434-442.
    • (2005) IEEE Design &Test of Computers , pp. 434-442
    • Murali, S.1
  • 9
    • 38749126805 scopus 로고    scopus 로고
    • Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Forward Error Correction Coding
    • P. P. Pande, et al., "Design of Low Power & Reliable Networks on Chip Through Joint Crosstalk Avoidance and Forward Error Correction Coding", in Proc. of IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT'06), 2006, pp. 466-476.
    • (2006) Proc. of IEEE Int'l Symp. on Defect and Fault Tolerance in VLSI Systems (DFT'06) , pp. 466-476
    • Pande, P.P.1
  • 11
    • 39749110032 scopus 로고    scopus 로고
    • Dependable Network-on-Chip Router Able to Simultaneously Tolerate Soft Errors and Crosstalk
    • A. Frantz, F. Kastensmidt, L. Carro, E. Cota, "Dependable Network-on-Chip Router Able to Simultaneously Tolerate Soft Errors and Crosstalk", in Proc. of IEEE Int'l Test Conf., 2006, pp. 1-9.
    • (2006) Proc. of IEEE Int'l Test Conf , pp. 1-9
    • Frantz, A.1    Kastensmidt, F.2    Carro, L.3    Cota, E.4
  • 12
    • 21244433563 scopus 로고    scopus 로고
    • M. Coppola, R. Locatelli, G. Maruccia, L. Pieralisi, A. Scandurra, Spidergon: A Novel On-Chip Communication Network, IEEE Proc. Int'l Symp. on System-on-Chip, 2004, 16-18 Nov., 2004, p. 15.
    • M. Coppola, R. Locatelli, G. Maruccia, L. Pieralisi, A. Scandurra, "Spidergon: A Novel On-Chip Communication Network", IEEE Proc. Int'l Symp. on System-on-Chip, 2004, 16-18 Nov., 2004, p. 15.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.