Adaptive stochastic routing in fault-tolerant on-chip networks

Proceedings - 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip, NoCS 2009

Volumn , Issue , 2009, Pages 32-37

  Song, Wei ^a   Edwards, Doug ^a   Nuñez Yañez, José Luis ^b   Dasgupta, Sohini ^a  

^a UNIVERSITY OF MANCHESTER   (United Kingdom)

^b UNIVERSITY OF BRISTOL   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

CONNECTION ORIENTED; DYNAMIC RE-CONFIGURATION; FAULT-TOLERANT; LEARNING PROCEDURES; NETWORK STATUS; ON-CHIP CIRCUITS; ON-CHIP NETWORKS; PATH RESERVATION; PROBABILITY MODELS; ROUTING TABLE; SELF-LEARNING MECHANISM;

BIOLOGICAL MATERIALS; DYNAMIC MODELS; ELECTRIC NETWORK TOPOLOGY; ERRORS; FAULT TOLERANCE; LEARNING ALGORITHMS; NETWORKS (CIRCUITS); QUALITY ASSURANCE; REMELTING; ROUTERS; SIMULATORS;

ROUTING ALGORITHMS;

EID: 70349826940     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2009.5071442     Document Type: Conference Paper

References (9)

1. J. Bainbridge and S. Furber. Chain: a delay-insensitive chip area interconnect. IEEE Micro, 22:16-23, 2002.
2. D. Bertozzi, L. Benini, and G. D. Micheli. Error control schemes for on-chip communication links: the energy-reliability tradeoff. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 24(6):818-831, June 2005.
3. P. Bogdan and R. Marculescu. A theoretical framework for on-chip stochastic communication analysis. In Proceedings of the International Conference on Nano-Networks and Workshops, 2006.
4. C. Constantinescu. Trends and challenges in VLSI circuit reliability. IEEE Micro, 23(4): 14-19, July 2003.
5. T. Dumitras and R. Marculescu. On-chip stochastic communication. In Proc of DATE, 2003.
6. S. Hollis and S. W. Moore. RasP: an area-efficient, on-chip network. In Proc of ICCD, pages 63-69, October 2006.
7. J. L. Nunez-Yanez, D. Edwards, and A. M. Coppola. Adaptive routing strategies for fault-tolerant on-chip networks in dynamically reconfigurable systems. IET Computers & Digital Techniques, 2(3):184-198, May 2008.
8. M. Pirretti, G. M. Link, R. R. Brooks, N. Vijaykrishnan, M. Kandemir, and M. J. Irwin. Fault tolerant algorithms for network-on-chip interconnect. In Proceedings of the IEEE Computer society Annual Symposium on VLSI, 2004.
9. H. Zimmer and A. Jantsch. A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip. In Proc of CODES+ISSS, pages 188-193, October 2003.