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Volumn , Issue , 2010, Pages 396-401

Crosstalk modeling to predict channel delay in Network-on-Chips

Author keywords

[No Author keywords available]

Indexed keywords

ANALYTICAL MODEL; CHANNEL DELAY; COMMUNICATION CHANNEL; CROSSTALK FAULT; CROSSTALK MITIGATION; EVALUATION PHASE; NANO-SCALE VLSI; NETWORK-ON-CHIPS; SPICE SIMULATIONS; THREE ORDERS OF MAGNITUDE; TIMING DELAY; TRANSITION PATTERNS; WORKING CONDITIONS;

EID: 78650747463     PISSN: 10636404     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ICCD.2010.5647684     Document Type: Conference Paper
Times cited : (10)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.