Design of low power & reliable networks on chip through joint crosstalk avoidance and forward error correction coding

Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

Volumn , Issue , 2006, Pages 466-474

  Pande, Partha Pratim ^a   Ganguly, Amlan ^a   Feero, Brett ^a   Belzer, Benjamin ^a   Grecu, Cristian ^b  

^a Washington State University   (United States)

^b UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

DATA TRANSFER; ERROR CORRECTION; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; PACKET NETWORKS; RELIABILITY; SWITCHING NETWORKS;

COMMUNICATION ARCHITECTURES; CROSSTALK AVOIDANCE CODING (CAC);

COMMUNICATION SYSTEMS;

EID: 38749126805     PISSN: 15505774     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DFT.2006.22     Document Type: Conference Paper

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