Addressing signal integrity in networks on chip interconnects through crosstalk-aware double error correction coding

Proceedings - IEEE Computer Society Annual Symposium on VLSI: Emerging VLSI Technologies and Architectures

Volumn , Issue , 2007, Pages 317-322

  Ganguly, Amlan ^a   Pande, Partha Pratim ^a   Belzer, Benjamin ^a   Grecu, Cristian ^b  

^a Washington State University   (United States)

^b UNIVERSITY OF BRITISH COLUMBIA   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CROSSTALK; ELECTRIC NETWORK ANALYSIS; ERROR CORRECTION; MICROPROCESSOR CHIPS; PACKET NETWORKS; SIGNAL ENCODING;

NETWORKS ON CHIP INTERCONNECTS; NOC INTERCONNECT INFRASTRUCTURES; SIGNAL INTEGRITY; TRANSIENT MALFUNCTIONS;

INTERCONNECTION NETWORKS;

EID: 36348945646     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISVLSI.2007.21     Document Type: Conference Paper

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