Modeling the effect of technology trends on the soft error rate of combinational logic

Proceedings of the 2002 International Conference on Dependable Systems and Networks

Volumn , Issue , 2002, Pages 389-398

  Shivakumar, Premkishore ^a   Kistler, Michael ^a,b   Keckler, Stephen W ^a   Burger, Doug ^a   Alvisi, Lorenzo ^a  

^a The University of Texas at Austin ^*  (United States)

^b IBM AUSTIN RESEARCH LABORATORY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMBINATIONAL LOGIC; ELECTRICAL MASKING; INSTRUCTION LEVEL PARALLELISM; LATCHING WINDOW MASKING; SOFT ERROR RATES;

CMOS INTEGRATED CIRCUITS; COMBINATORIAL CIRCUITS; COMPUTER SIMULATION; ELECTRIC INVERTERS; INTEGRATED CIRCUIT LAYOUT; NEUTRONS; PARALLEL PROCESSING SYSTEMS; PIPELINE PROCESSING SYSTEMS; STATIC RANDOM ACCESS STORAGE;

MICROPROCESSOR CHIPS;

EID: 0036931372     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DSN.2002.1028924     Document Type: Conference Paper

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