Self-adaptive system for addressing permanent errors in on-chip interconnects

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 18, Issue 4, 2010, Pages 527-540

  Lehtonen, Teijo ^a,b   Wolpert, David ^c   Liljeberg, Pasi ^b   Plosila, Juha ^b,d   Ampadu, Paul ^c  

^a TURKU CENTRE FOR COMPUTER SCIENCE   (Finland)

^b UNIVERSITY OF TURKU   (Finland)

^c University of Rochester   (United States)

^d ACADEMY OF FINLAND   (Finland)

Author keywords

Adaptive systems; Digital systems; Fault tolerance; Forward error correction (FEC); Integrated circuit interconnections; Networks on chip (NoCs); Reliability; Self testing

Indexed keywords

DIGITAL SYSTEM; DIGITAL SYSTEMS; INTEGRATED CIRCUIT INTERCONNECTIONS; NETWORKS ON CHIPS; NETWORKS-ON-CHIP (NOCS); SELF-TESTING;

ADAPTIVE SYSTEMS; BIOLOGICAL MATERIALS; DIGITAL INTEGRATED CIRCUITS; ERROR CORRECTION; FAULT TOLERANCE; INTEGRATED CIRCUIT TESTING; INTEGRATED CIRCUITS; INTERCONNECTION NETWORKS; QUALITY ASSURANCE; WIRE;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 77950301257     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2009.2013711     Document Type: Article

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