On hamming product codes with type-II hybrid ARQ for on-chip interconnects

IEEE Transactions on Circuits and Systems I: Regular Papers

Volumn 56, Issue 9, 2009, Pages 2042-2054

  Fu, Bo ^a   Ampadu, Paul ^a  

^a University of Rochester   (United States)

Author keywords

Error control; Hamming product codes; On chip interconnects; Reliability; Type II hybrid ARQ

Indexed keywords

CODES (SYMBOLS); ENERGY UTILIZATION; ERROR CORRECTION; INVENTORY CONTROL; NETWORK-ON-CHIP; RELIABILITY;

ERROR CONTROL; H.264 VIDEO ENCODER; HAMMING PRODUCT CODES; HARDWARE PERFORMANCE ANALYSIS; HYBRID AUTOMATIC REPEAT REQUEST; ON-CHIP INTERCONNECTS; ORDERS OF MAGNITUDE; TYPE-II HYBRID ARQ;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 70349257426     PISSN: 15498328     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSI.2009.2026679     Document Type: Article

References (32)

1. C. Constantinescu, "Trends and challenges in VLSI circuit reliability," IEEE Micro, vol. 23, no. 4, pp. 14-19, Jul./Aug. 2003.
2. M. Lajolo, M. Reorda, and M. Violante, "Early evaluation of bus interconnects dependability for system-on-chip designs," in Int. Conf. VLSI Design, Jan. 2001, pp. 371-376.
3. G. De Micheli and L. Benini, Networks on Chips: Technology and Tools Amsterdam, The Netherlands: Elsevier, 2006.
4. J. A. Davis and R. VenkatesanA. KaloyerosM. Beylansky, S. J. Souri, K. Banerjee, K. C. Saraswat, A. Rahman, R. Reif, and J. D. Meindl, "Interconnect limits on gigascale integration (GSI) in the 21st century," in Proc. IEEE, Mar. 2001, vol. 89, no. 3, pp. 305-324.
5. F. Caignet, S. D. Bendhia, and E. Sicard, "The challenge of signal integrity in deep-submicrometer CMOS technology," in Proc. IEEE, Apr. 2001, vol. 89, no. 4, pp. 556-573.
6. D. Bertozzi, L. Benini, and G. De Micheli, "Error control schemes for on-chip communication links: The energy-reliability tradeoff," IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 24, pp. 818-831, Jun. 2005.
7. S. Sridhara and N. R. Shanbhag, "Coding for system-on-chip networks: A unified framework," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, pp. 655-667, Jun. 2005.
8. S. Murali, T. Theocharides, N. Vijaykrishnan, M. J. Irwin, L. Benini, and G. De Micheli, "Analysis of error recovery schemes for networks-on-chips," IEEE Des. Test Comput., vol. 22, pp. 434-442, Sep./Oct. 2005.
9. A. Ejlali, B. M. Al-Hashimi, P. Rosinger, and S. G. Miremadi, "Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks," in Proc. Des., Autom. Test Eur. Conf. Exhib. (DATE 2007), Apr., pp. 1-6.
10. D. Rossi, A. K. Nieuwland, S. V. E. van Dijk, R. P. Kleihorst, and C. Metra, "Power consumption of fault tolerant busses," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 16, pp. 542-553, May 2008.
11. H. Zimmer and A. Jantsch, "A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip," in Proc. CODES-ISSS Conf., Oct. 2003, pp. 188-193.
12. Q. Yu and P. Ampadu, "Adaptive error control for NoC switch-to-switch links in a variable noise environment," in Proc. IEEE Int. Symp. Defect Fault Tolerance VLSI Syst. (DFT 2008 ), Oct., pp. 352-360.
13. D. Rossi, P. Angelini, and C. Metra, "Configurable error control scheme for NoC signal integrity," in Proc. Int. Line Testing Symp. (IOLTS) July 2007, pp. 43-48.
14. A. Ganguly, P. P. Pande, B. Belzer, and C. Grecu, "Design of low power & reliable networks on chip through joint crosstalk avoidance and multiple error correction coding," J. Electron. Testing: Theory Appl. (JETTA), Special Issue on Defect Fault Tolerance, pp. 67-81, Jun. 2008.
15. T. Lehtonen, P. Liljeberg, and J. Plosila, "Analysis of forward error correction methods for nanoscale networks-on-chip," in Proc. 2nd Int. Conf. Nano-Networks (Nano-Net 2007), Sep., pp. 1-5.
16. B. Fu and P. Ampadu, "A multiple-wire error correction scheme for reliable and energy efficient SoC links using Hamming product codes," in Proc. IEEE Int. SOC Conf. (SOCC), Sept. 2008, pp. 15-19.
17. B. Fu and P. Ampadu, "An energy-efficient multi-wire error control scheme for reliable on-chip interconnects using Hamming product codes," VLSI Des., vol. 2008, pp. 1-14, 2008, doi:10.1155/2008/109490, article ID: 109490,.
18. R. Pyndiah, "Near-optimum decoding of product codes: Block turbo codes," IEEE Trans. Commun., vol. 46, no. 8, pp. 1003-1010, Aug. 1998.
19. F. Chiaraluce and R. Garello, "Extended Hamming product codes analytical performance evaluation for low error rate applications," IEEE Trans. Wireless Commun., vol. 3, pp. 2353-2361, Nov. 2004.
20. S. Lin, D. J. Costello, and M. J. Miller, "Automatic-repeat-request error-control schemes," IEEE Commun. Mag., vol. 22, no. 12, pp. 5-17, Dec. 1984.
21. S. Lin and D. J. Costello, Error Control Coding, 2nd ed. Englewood Cliffs, NJ: Prentice Hall, 2004.
22. R. Hegde and N. R. Shanbhag, "Towards achieving energy-efficiency in presence of deep submicron noise," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 8, pp. 379-391, Aug. 2000.
23. P. P. Pande, C. Grecu, A. Ivanov, and R. Saleh, "Performance evaluation and design trade-offs for network-on-chip interconnect architectures," IEEE Trans. Comput., vol. 54, no. 8, pp. 1025-1040, Aug. 2005.
24. F. Worm, P. Ienne, P. Thiran, and G. D. Micheli, "A robust self-calibrating transmission scheme for on-chip networks," IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 13, no. 1, pp. 126-139, Jan. 2005.
25. D. Bertozzi and L. Benini, "Xpipes: A network-on-chip architecture for gigascale systems-on-chip," IEEE Circuits Syst. Mag., vol. 4, pp. 18-31, Jun. 2004.
26. Arizona State Univ., Tempe, "Predictive technology model," [Online]. Available: http://www.eas.asu.edu/~ptm/
27. S. Xu, I. Benito, and W. Burleson, "Thermal impacts on NoC interconnects," in Proc. IEEE Int. Symp. Networks-on-Chip (NOCS 2007), May, pp. 220-220 [Online]. Available: http:// python.ecs.umass.edu/~icdg/publications/pdffiles/xu_noc07.pdf, Full version available:
28. J. S. Kim, M. B. Taylor, J. Miller, and D. Wentzlaff, "Energy characterization of a tiled architecture processor with on-chip networks," in Proc. Int. Symp. Low Power Electron. Des. (ISLPED 2003), Aug., pp. 424-427.
29. S. R. Vangal, J. Howard, G. Ruhl, S. Dighe, H. Wilson, T. Tschanz, D. Finan, A. Singh, T. Jacob, S. Jain, V. Erraguntla, C. Roberts, Y. Joskote, N. Borkar, and S. Borkar, "An 80-tile sub-100-W teraFLOPS processor in 65-nm CMOS," IEEE J. Solid-State Circuits, vol. 43, no. 1, pp. 29-41, Jan. 2008.
30. M. Ghoneima, Y. Ismail, M. Khellah, and V. De, "SSMCB: Low-power variation-tolerant source-synchronous multicycle bus," IEEE Trans. Circuits Syst. I, vol. 56, no. 2, pp. 384-394, Feb. 2009.
31. V. Adler and E. G. Friedman, "Repeater design to reduce delay and power in resistive interconnect," IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 5, pp. 607-616, May 1998.
32. M. D. Shieh, M. H. Sheu, C. H. Chen, and H. F. Lo, "A systematic approach for parallel CRC computations," J Inf. Sci. Eng., vol. 17, pp. 445-461, May 2001.