An 80-Tile 1.28TFLOPS network-on-chip in 65nm CMOS

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn , Issue , 2007, Pages

  Vangal, Sriram ^a,b   Howard, Jason ^a   Ruhl, Gregory ^a   Dighe, Saurabh ^a   Wilson, Howard ^a   Tschanz, James ^a   Finan, David ^a   Iyer, Priya ^a   Singh, Arvind ^a   Jacob, Tiju ^a   Jain, Shailendra ^a   Venkataraman, Sriram ^a   Hoskote, Yatin ^a   Borkar, Nitin ^a  

^a INTEL CORPORATION   (United States)

^b LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; INTEGRATED CIRCUIT LAYOUT; NANOELECTRONICS; PACKET SWITCHING; ROUTERS; TRANSISTORS;

CLOCK GATING; MESOCHRONOUS CLOCKING; TRANSISTOR DIE;

CMOS INTEGRATED CIRCUITS;

EID: 34548858682     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2007.373606     Document Type: Conference Paper

References (6)

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2. S. Vangal, Y. Hoskote, N. Y. Borkar, et al., "A 6.2-GFlops Floating-Point Multiply-Accumulator with Conditional, Normalization," IEEE J. Solid-State Circuits, pp. 2314-2323, Oct., 2006.
3. S. Vangal, N. Y. Borkar, and A. Alvandpour, "A Six-Port 57GB/s Double-Pumped Non-blocking Router Core," Dig. Symp. VLSI Circuits, pp. 1268-269, June 2005.
4. 2 SRAM Cell,"' IEDM Tech. Dig., pp. 657-660, Dec., 2004.
5. J. Tschanz, S. G. Narendra, Y Ye, et al., "Dynamic Sleep Transistor and Body Bias for Active Leakage Power Control of Microprocessors," IEEE J. Solid-State Circuits, pp. 1838-1845, Nov. 2003.
6. 2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS," ISSCC Dig. Tech. Papers, pp. 624-625, Feb., 2006.