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Volumn , Issue , 2011, Pages 667-672

ReliNoC: A reliable network for priority-based on-chip communication

Author keywords

[No Author keywords available]

Indexed keywords

AREA OVERHEAD; CONTROL OVERHEAD; DATA PACKET; FAULTY ELEMENTS; INHERENT REDUNDANCY; LOW PRIORITIES; LOW-YIELD; NETWORK-ON-CHIP ARCHITECTURES; NETWORKS ON CHIPS; ON CHIP COMMUNICATION; PHYSICAL CHANNELS; PRIORITY-BASED; SCALED TECHNOLOGIES; SWITCH ARCHITECTURES; VIRTUAL CHANNELS;

EID: 79957548187     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (30)

References (27)
  • 1
    • 77955099370 scopus 로고    scopus 로고
    • Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-Processor Systems-on-Chip
    • F. Gilabert et al., "Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-Processor Systems-on-Chip," Proc. ACM/IEEE NoCS, pp. 165-172, 2010.
    • (2010) Proc. ACM/IEEE NoCS , pp. 165-172
    • Gilabert, F.1
  • 2
    • 78650744866 scopus 로고
    • The reliable router: A reliable and high-performance communication substrate for parallel computers
    • W. J. Dally et al. "The reliable router: A reliable and high-performance communication substrate for parallel computers," Proc. PCRCW, pp. 241-255, 1994.
    • (1994) Proc. PCRCW , pp. 241-255
    • Dally, W.J.1
  • 3
    • 33846493158 scopus 로고    scopus 로고
    • BulletProof: A defect-tolerant CMP switch architecture
    • K. Constantinides et al. "BulletProof: a defect-tolerant CMP switch architecture," Proc. IEEE HPCA, pp. 5-16, 2006.
    • (2006) Proc. IEEE HPCA , pp. 5-16
    • Constantinides, K.1
  • 4
    • 70350721929 scopus 로고    scopus 로고
    • Vicis: A Reliable Network for Unreliable Silicon
    • David Fick et al., "Vicis: A Reliable Network for Unreliable Silicon," Proc. ACM/IEEE DAC, pp. 812-817, 2009.
    • (2009) Proc. ACM/IEEE DAC , pp. 812-817
    • Fick, D.1
  • 5
    • 70350075849 scopus 로고    scopus 로고
    • A highly resilient routing algorithm for fault-tolerant NoCs
    • D. Fick et al.,"A highly resilient routing algorithm for fault-tolerant NoCs," Proc. ACM/IEEE DATE, pp. 21-26, 2009.
    • (2009) Proc. ACM/IEEE DATE , pp. 21-26
    • Fick, D.1
  • 6
    • 85008024848 scopus 로고    scopus 로고
    • An efficient fault-tolerant routing methodology for meshes and tori
    • M. E. Gomez et al., "An efficient fault-tolerant routing methodology for meshes and tori," IEEE Computer Architecture Letters, vol. 3, No. 1, pp. 3-3, 2004.
    • (2004) IEEE Computer Architecture Letters , vol.3 , Issue.1 , pp. 3-3
    • Gomez, M.E.1
  • 7
    • 77955109421 scopus 로고    scopus 로고
    • Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
    • S. Rodrigo et al., "Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing,", Proc. ACM/IEEE NoCS, pp. 25-32, 2010.
    • (2010) Proc. ACM/IEEE NoCS , pp. 25-32
    • Rodrigo, S.1
  • 8
    • 1942468128 scopus 로고    scopus 로고
    • A new approach to fault-tolerant wormhole routing for mesh-connected parallel computers
    • C.-T. Ho et al., "A new approach to fault-tolerant wormhole routing for mesh-connected parallel computers," IEEE Trans. on Computers, Vol. 53, No. 4, pp. 427-439, 2004.
    • (2004) IEEE Trans. on Computers , vol.53 , Issue.4 , pp. 427-439
    • Ho, C.-T.1
  • 9
    • 21644436489 scopus 로고    scopus 로고
    • Microarchitecture and design challenges for gigascale integration
    • keynote address
    • S. Borkar,"Microarchitecture and design challenges for gigascale integration," Proc. ACM/IEEE MICRO, keynote address, pp. 3-3, 2004.
    • (2004) Proc. ACM/IEEE MICRO , pp. 3-3
    • Borkar, S.1
  • 10
    • 44149094592 scopus 로고    scopus 로고
    • An efficient Implementation of Distributed Routing Algorithms for NoCs
    • J. Flich et al., "An efficient Implementation of Distributed Routing Algorithms for NoCs," Proc. ACM/IEEE NoCS, pp. 87-96 , 2008.
    • (2008) Proc. ACM/IEEE NoCS , pp. 87-96
    • Flich, J.1
  • 11
    • 84887445794 scopus 로고    scopus 로고
    • Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Model
    • A. Alaghi et al., "Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Model," Proc. IEEE DFT, pp. 21-29, 2007.
    • (2007) Proc. IEEE DFT , pp. 21-29
    • Alaghi, A.1
  • 12
    • 0025433355 scopus 로고
    • Virtual-Channel Flow Control
    • W.J.Dally "Virtual-Channel Flow Control," Proc. ACM/IEEE ISCA, pp. 60-68, 1990.
    • (1990) Proc. ACM/IEEE ISCA , pp. 60-68
    • Dally, W.J.1
  • 13
    • 33745800231 scopus 로고    scopus 로고
    • A survey of research and practices of network-on-chip
    • T. Bjerregaard et al., "A survey of research and practices of network-on-chip," ACM Computer Survey, Vol. 38, No. 1, 2006.
    • (2006) ACM Computer Survey , vol.38 , Issue.1
    • Bjerregaard, T.1
  • 14
    • 2942694701 scopus 로고    scopus 로고
    • A Power and Performance Model for Network-on-Chip Architectures
    • N.Banerjee et al., "A Power and Performance Model for Network-on-Chip Architectures," Proc. ACM/IEEE DATE, pp. 21250, 2004.
    • (2004) Proc. ACM/IEEE DATE , pp. 21250
    • Banerjee, N.1
  • 15
    • 34547348093 scopus 로고    scopus 로고
    • Virtual Channels in Networks-on-Chip: Implementation and Evaluation on Hermes NoC
    • A.Mello et al., "Virtual Channels in Networks-on-Chip: Implementation and Evaluation on Hermes NoC," Proc. ACM/IEEE SBCCI, pp. 178-183, 2005.
    • (2005) Proc. ACM/IEEE SBCCI , pp. 178-183
    • Mello, A.1
  • 16
    • 46249102743 scopus 로고    scopus 로고
    • Multiplane Virtual Channel Router for Network-on-Chip Design
    • S.Noh et al. "Multiplane Virtual Channel Router for Network-on-Chip Design," Proc. IEEE ICCE, pp. 348-351, 2006.
    • (2006) Proc. IEEE ICCE , pp. 348-351
    • Noh, S.1
  • 17
    • 77952943435 scopus 로고    scopus 로고
    • Virtual channels vs. multiple physical networks: A comparative analysis
    • Young Jin Yoon et al."Virtual channels vs. multiple physical networks: a comparative analysis," Proc. ACM/IEEE DAC, PP. 162-165, 2010.
    • (2010) Proc. ACM/IEEE DAC , pp. 162-165
    • Yoon, Y.J.1
  • 19
    • 25144518593 scopus 로고    scopus 로고
    • Process variation in embedded memories: Failure analysis and variation aware architecture
    • A. Agarwal et al., "Process variation in embedded memories: Failure analysis and variation aware architecture," IEEE J. Solid-State Circuits, Vol. 40, No. 9, pp. 1804-1814, 2005.
    • (2005) IEEE J. Solid-State Circuits , vol.40 , Issue.9 , pp. 1804-1814
    • Agarwal, A.1
  • 20
    • 34047143799 scopus 로고    scopus 로고
    • A Concurrent Testing Method for NoC Switches
    • M. Hosseinabadi et al., "A Concurrent Testing Method for NoC Switches," Proc. ACM/IEEE DATE, pp. 1171-1176, 2006.
    • (2006) Proc. ACM/IEEE DATE , pp. 1171-1176
    • Hosseinabadi, M.1
  • 21
    • 4043150092 scopus 로고    scopus 로고
    • Xpipes:A network-on-chip architecture for gigascale system-on-chip
    • D. Bertozzi et al., "Xpipes:A network-on-chip architecture for gigascale system-on-chip," IEEE Circuits Syst. Mag., Vol. 4, No. 2, pp. 18-31, 2004.
    • (2004) IEEE Circuits Syst. Mag. , vol.4 , Issue.2 , pp. 18-31
    • Bertozzi, D.1
  • 22
    • 77954526063 scopus 로고    scopus 로고
    • A new physical routing approach for robust bundled signaling on NoC links
    • M. R. Kakoee et al., "A new physical routing approach for robust bundled signaling on NoC links," Proc. ACM/IEEE GLSVLSI, pp. 3-8, 2010.
    • (2010) Proc. ACM/IEEE GLSVLSI , pp. 3-8
    • Kakoee, M.R.1
  • 24
    • 63549095070 scopus 로고    scopus 로고
    • The PARSEC benchmark suite: Characterization and architectural implications
    • Christian Bienia et al., "The PARSEC benchmark suite: characterization and architectural implications," Proc. ACM PACT, pp. 72-81, 2008.
    • (2008) Proc. ACM PACT , pp. 72-81
    • Bienia, C.1
  • 25
    • 0036469676 scopus 로고    scopus 로고
    • Simics: A full system simulation platform
    • P. S. Magnusson et al., "Simics: A full system simulation platform," IEEE Computer, Vol. 35, No. 2, pp. 50-58, 2002.
    • (2002) IEEE Computer , vol.35 , Issue.2 , pp. 50-58
    • Magnusson, P.S.1
  • 26
    • 33748870886 scopus 로고    scopus 로고
    • Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset
    • M. M. K. Martin et al., "Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset," SIGARCH Computer Architecture News, Vol. 33, No. 4, pp. 92-99, 2005.
    • (2005) SIGARCH Computer Architecture News , vol.33 , Issue.4 , pp. 92-99
    • Martin, M.M.K.1
  • 27
    • 70049105948 scopus 로고    scopus 로고
    • GARNET: A detailed on-chip network model inside a full-system simulator
    • L.-S. Peh et al., "GARNET: A detailed on-chip network model inside a full-system simulator," Proc. IEEE ISPASS, pp. 33-42, 2009.
    • (2009) Proc. IEEE ISPASS , pp. 33-42
    • Peh, L.-S.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.