Investigation of transient fault effects in synchronous and asynchronous network on chip router

Journal of Systems Architecture

Volumn 57, Issue 1, 2011, Pages 61-68

  Yaghini, Pooria M ^a   Eghbal, Ashkan ^a   Pedram, Hossein ^a   Zarandi, Hamid Reza ^a  

^a AMIRKABIR UNIVERSITY OF TECHNOLOGY   (Iran)

Author keywords

Asynchronous and synchronous design; Fault injection; Fault tolerance evaluation; Network on chip router

Indexed keywords

ASYNCHRONOUS AND SYNCHRONOUS DESIGN; ASYNCHRONOUS DESIGN; ASYNCHRONOUS NETWORKS; FAILURE RATE; FAULT INJECTION; FAULT INJECTOR; FAULT MODEL; FAULT PROPAGATION; FAULT-TOLERANT; NETWORK ON CHIP; SIMULATION-BASED; TRANSIENT FAULTS;

ASYNCHRONOUS SEQUENTIAL LOGIC; DESIGN; EXPERIMENTS; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; MICROPROCESSOR CHIPS; NETWORK ARCHITECTURE; RANDOM ACCESS STORAGE; ROUTERS; TRANSIENTS;

QUALITY ASSURANCE;

EID: 78650281499     PISSN: 13837621     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.sysarc.2010.10.003     Document Type: Article

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