Low-power and error protection coding for network-on-chip traffic

IET Computers and Digital Techniques

Volumn 2, Issue 6, 2008, Pages 483-492

  Vitkovski, A ^a   Jantsch, A ^b   Lauter, R ^b   Haukilahti, R ^b   Nilsson, E ^b  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRIC BREAKDOWN; ELECTRIC NETWORK TOPOLOGY; ELECTRIC POWER UTILIZATION; ENCODING (SYMBOLS); MICROPROCESSOR CHIPS; NETWORK PROTOCOLS; PROGRAMMING THEORY; SENSOR NETWORKS; SWITCHES;

DATA LINKS; DATA PROTECTIONS; ENCODING; ENCODING SCHEMES; ERROR PROTECTIONS; ERROR RATES; LOGIC BLOCKS; LOW-POWER; LOWER VOLTAGES; NETWORK LAYERS; NETWORK-ON-CHIP; POWER ANALYSES; POWER CONSUMPTIONS; ROUTING SWITCHES;

COMPUTER NETWORKS;

EID: 54949138429     PISSN: 17518601     EISSN: None     Source Type: Journal    
DOI: 10.1049/iet-cdt:20050060     Document Type: Article

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