Addressing manufacturing challenges with cost-efficient fault tolerant routing

NOCS 2010 - The 4th ACM/IEEE International Symposium on Networks-on-Chip

Volumn , Issue , 2010, Pages 25-32

  Rodrigo, S ^a   Flich, J ^a   Roca, A ^a   Medardoni, S ^b   Bertozzi, D ^b   Camacho, J ^a   Silla, F ^a   Duato, J ^a  

^a UNIVERSITAT POLITÈCNICA DE VALÈNCIA   (Spain)

^b UNIVERSITY OF FERRARA   (Italy)

Author keywords

Fault tolerance; Networks on chip; Routing

Indexed keywords

COST-EFFICIENT; DISTRIBUTED ROUTING; EFFICIENT ROUTING; FAULT TOLERANT ROUTING; HIGH-PERFORMANCE COMPUTING; IRREGULAR TOPOLOGY; KEY COMPONENT; LATENCY CONSTRAINTS; MANUFACTURING CHALLENGES; MANY-CORE; NETWORKS ON CHIPS; PERFORMANCE COSTS; POWER-AWARE; ROUTING TABLE; UNIVERSAL LOGIC;

CONCENTRATION (PROCESS); MICROPROCESSOR CHIPS; QUALITY ASSURANCE; TELECOMMUNICATION NETWORKS; TOPOLOGY;

FAULT TOLERANCE;

EID: 77955109421     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2010.12     Document Type: Conference Paper

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