Crosstalk- and SEU-aware networks on chips

IEEE Design and Test of Computers

Volumn 24, Issue 4, 2007, Pages 340-350

  Frantz, Arthur Pereira ^a   Cassel, Maico ^b   Kastensmidt, Fernanda Lima ^b   Cota, Érika ^b   Carro, Luigi ^b  

^a Datacom Telecommunications ^*

^b FEDERAL UNIVERSITY OF RIO GRANDE DO SUL   (Brazil)

Author keywords

Crosstalk; Fault tolerance. energy aware systems; Hardware software codesign; Network on chip; Single event upset

Indexed keywords

COST-EFFECTIVE SOLUTIONS; CROSSTALK EFFECTS; CROSSTALK FAULTS; HARDWARE AND SOFTWARES; HARDWARE-SOFTWARE CODESIGN; MITIGATION TECHNIQUES; NETWORK ON CHIP; NETWORKS ON CHIPS; ON-CHIP NETWORKS; SINGLE-EVENT UPSET; SOFTWARE SOLUTIONS; SOFTWARE-BASED SOLUTIONS;

CROSSTALK; DIGITAL STORAGE; ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK TOPOLOGY; FAULT TOLERANCE; FAULT TOLERANT COMPUTER SYSTEMS; FLASH MEMORY; HARDWARE; MICROPROCESSOR CHIPS; QUALITY ASSURANCE; URANIUM POWDER METALLURGY;

ROUTERS;

EID: 44149107193     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2007.128     Document Type: Article

References (10)

1. A. Acquaviva and A. Bogliolo, "A Bottom-Up Approach to On-Chip Signal Integrity," Proc. Integrated Circuit and System Design, LNCS 2799, Springer, 2003, pp. 540-549.
2. A.K. Nieuwland et al., "Coding Techniques for Low Switching Noise in Fault Tolerant Busses," Proc. 11th IEEE Int'l On-Line Testing Symp. (IOLTS 05), IEEE Press, 2005, pp. 183-189.
3. R.R. Tamhankar, S. Murali, and G. De Micheli, "Performance Driven Reliable Link Design for Networks on Chips," Proc. Asia and South Pacific Design Automation Conf. (ASP-DAC 05), ACM Press, 2005, vol. 2, pp. 749-754.
4. M. Nicolaidis, "Design for Soft Error Mitigation," IEEE Trans. Device and Materials Reliability, vol. 5, no. 3, Sept. 2005, pp. 405-418.
5. D. Rossi et al., "Exploiting ECC Redundancy to Minimize Crosstalk Impact," IEEE Design & Test, vol. 22, no. 1, Jan.-Feb. 2005, pp. 59-70.
6. D. Bertozzi, L. Benini, and G. De Micheli, "Low Power Error Resilient Encoding for On-Chip Data Buses," Proc. Design, Automation and Test in Europe Conf. (DATE 02), IEEE CS Press, 2002, pp. 102-109.
7. S. Mitra et al., "Robust System Design with Built-in Soft-Error Resilience," Computer, vol. 38, no. 2, Feb. 2005, pp. 43-52.
8. A.P. Frantz et al., "Dependable Network-on-Chip Router Able to Simultaneously Tolerate Soft Errors and Crosstalk," Proc. IEEE Int'l Test Conf. (ITC 06), IEEE CS Press, 2006, pp. 15.2.1-15.2.9.
9. C.A. Zeferino and A.A. Susin, "SoCIN: A Parametric and Scalable Network-on-Chip," Proc. 16th Symp. Integrated Circuits and Systems Design (SBCCI), IEEE CS Press, 2003, pp. 169-174.
10. M. Cuviello et al., "Fault Modeling and Simulation for Crosstalk in System-on-Chip Interconnects," Proc. IEEE/ACM Int'l Conf. Computer-Aided Design (ICCAD 99), IEEE CS Press, 1999, pp. 297-303.