메뉴 건너뛰기




Volumn 38, Issue 1, 2006, Pages 71-121

A survey of research and practices of network-on-chip

Author keywords

Chip area networks; Communication abstractions; Communication centric design; GALS; GSI design; Interconnects; Network on chip; NoC; OCP; On chip communication; SoC; Sockets; System on chip; ULSI design

Indexed keywords

CHIP-AREA NETWORKS; COMMUNICATION ABSTRACTIONS; COMMUNICATION-CENTRIC DESIGN; GALS; GSI DESIGN; NETWORK-ON-CHIP (NOC); ON-CHIP COMMUNICATION (OCP); SOCKETS; SYSTEMS-ON-CHIP (SOC).; ULSI DESIGN;

EID: 33745800231     PISSN: 03600300     EISSN: 03600300     Source Type: Journal    
DOI: None     Document Type: Review
Times cited : (848)

References (154)
  • 1
    • 0002681039 scopus 로고    scopus 로고
    • The Oxygen project - Raw computation
    • AGARWAL, A. 1999. The Oxygen project - Raw computation. Scientific American, 44-47.
    • (1999) Scientific American , pp. 44-47
    • Agarwal, A.1
  • 2
    • 33745778388 scopus 로고    scopus 로고
    • Hierarchical interconnects for on-chip clustering
    • IEEE Computer Society
    • AGGARWAL, A. AND FRANKLIN, M. 2002. Hierarchical interconnects for on-chip clustering. In Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS). IEEE Computer Society, 602-609.
    • (2002) Proceedings of the , vol.16 , pp. 602-609
    • Aggarwal, A.1    Franklin, M.2
  • 4
    • 0031094579 scopus 로고    scopus 로고
    • A survey and comparison of wormhole routing techniques in a mesh networks
    • AL-TAWIL, K. M., ABD-EL-BARR, M., AND ASHRAF, F. 1997. A survey and comparison of wormhole routing techniques in a mesh networks. IEEE Network 11, 38-45.
    • (1997) IEEE Network , vol.11 , pp. 38-45
    • Al-Tawil, K.M.1    Abd-El-Barr, M.2    Ashraf, F.3
  • 6
    • 33745791682 scopus 로고    scopus 로고
    • On improving best-effort throughput by better utilization of guaranteed-throughput channels in an on-chip communication system
    • ANDREASSON, D. AND KUMAR, S. 2004. On improving best-effort throughput by better utilization of guaranteed-throughput channels in an on-chip communication system. In Proceeding of 22th IEEE Norchip Conference.
    • (2004) Proceeding of 22th IEEE Norchip Conference.
    • Andreasson, D.1    Kumar, S.2
  • 10
    • 84858917382 scopus 로고    scopus 로고
    • A comparison of network-on-chip and busses
    • ARTERIS. 2005. A comparison of network-on-chip and busses. White paper. http://www.arteris.com/noc_whitepaper.pdf.
    • (2005) White Paper
  • 12
    • 0036761283 scopus 로고    scopus 로고
    • CHAIN: A delay-insensitive chip area interconnect
    • BAINBRIDGE, J. AND FURBER, S. 2002. CHAIN: A delay-insensitive chip area interconnect. IEEE Micro 22, 5 (Oct.) 16-23.
    • (2002) IEEE Micro , vol.22 , Issue.5 OCT , pp. 16-23
    • Bainbridge, J.1    Furber, S.2
  • 17
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: A new SoC paradigm
    • BENINI, L. AND MICHELI, G. D. 2002. Networks on chips: A new SoC paradigm. IEEE Comput. 35, 1 (Jan.), 70-78.
    • (2002) IEEE Comput. , vol.35 , Issue.1 JAN , pp. 70-78
    • Benini, L.1    Micheli, G.D.2
  • 26
    • 1242309790 scopus 로고    scopus 로고
    • QNoC: QoS architecture and design process for network-on-chip
    • BOLOTIN, E., CIDON, I., GINOSAUR, R., AND KOLODNY, A. 2004. QNoC: QoS architecture and design process for network-on-chip. J. Syst. Archit. 50, 2-3, 105-128.
    • (2004) J. Syst. Archit. , vol.50 , Issue.2-3 , pp. 105-128
    • Bolotin, E.1    Cidon, I.2    Ginosaur, R.3    Kolodny, A.4
  • 29
    • 0034853842 scopus 로고    scopus 로고
    • Robust interfaces for mixed-timing systems with application to latency-insensitive protocols
    • IEEE
    • CHELCEA, T. AND NOWICK, S. M. 2001. Robust interfaces for mixed-timing systems with application to latency-insensitive protocols. In Proceedings of the 38th Design Automation Conference (DAC). IEEE, 21-26.
    • (2001) Proceedings of the 38th Design Automation Conference (DAC) , pp. 21-26
    • Chelcea, T.1    Nowick, S.M.2
  • 30
    • 0034226899 scopus 로고    scopus 로고
    • The odd-even turn model for adaptive routing
    • CHIU, G.-M. 2000. The odd-even turn model for adaptive routing. IEEE Trans. Parall. Distrib. Syst. 11, 729-738.
    • (2000) IEEE Trans. Parall. Distrib. Syst. , vol.11 , pp. 729-738
    • Chiu, G.-M.1
  • 31
    • 0035251054 scopus 로고    scopus 로고
    • On the benefit of supporting virtual channels in wormhole routers
    • COLE, R. J., MAGGS, B. M., AND SITARAMAN, R. K. 2001. On the benefit of supporting virtual channels in wormhole routers. J. Comput. Syst. Sciences 62, 152-177.
    • (2001) J. Comput. Syst. Sciences , vol.62 , pp. 152-177
    • Cole, R.J.1    Maggs, B.M.2    Sitaraman, R.K.3
  • 33
    • 0025448089 scopus 로고
    • Performance analysis of k-ary n-cube interconnection networks
    • DALLY, W. J. 1990. Performance analysis of k-ary n-cube interconnection networks. IEEE Trans. Comput. 39, 6 (June) 775-785.
    • (1990) IEEE Trans. Comput. , vol.39 , Issue.6 JUNE , pp. 775-785
    • Dally, W.J.1
  • 34
    • 0026825968 scopus 로고
    • Virtual-channel flow control
    • DALLY, W. J. 1992. Virtual-channel flow control. IEEE Trans. Parall. Distrib. Syst. 3, 2 (March) 194-205.
    • (1992) IEEE Trans. Parall. Distrib. Syst. , vol.3 , Issue.2 MARCH , pp. 194-205
    • Dally, W.J.1
  • 35
    • 0027579765 scopus 로고
    • Deadlock-free adaptive routing in multicomputer networks using virtual channels
    • DALLY, W. J. AND AOKI, H. 1993. Deadlock-free adaptive routing in multicomputer networks using virtual channels. IEEE Trans. Parall. Distrib. Syst. 4, 4 (April) 466-475.
    • (1993) IEEE Trans. Parall. Distrib. Syst. , vol.4 , Issue.4 APRIL , pp. 466-475
    • Dally, W.J.1    Aoki, H.2
  • 36
    • 0023346637 scopus 로고
    • Deadlock-free message routing in multiprocessor interconnection networks
    • DALLY, W. J. AND SEITZ, C. L. 1987. Deadlock-free message routing in multiprocessor interconnection networks. IEEE Trans. Comput. 36, 5 (May) 547-553.
    • (1987) IEEE Trans. Comput. , vol.36 , Issue.5 MAY , pp. 547-553
    • Dally, W.J.1    Seitz, C.L.2
  • 38
    • 48049124464 scopus 로고    scopus 로고
    • Evaluation of routing algorithms on mesh based noes
    • Faculdade de Informatica PUCRS - Brazil
    • DE MELLO, A. V., OST, L. C., MORAES, P. G., AND CALAZANS, N. L. V. 2004. Evaluation of routing algorithms on mesh based noes. Tech. rep., Faculdade de Informatica PUCRS - Brazil.
    • (2004) Tech. Rep.
    • De Mello, A.V.1    Ost, L.C.2    Moraes, P.G.3    Calazans, N.L.V.4
  • 41
    • 0029409835 scopus 로고
    • Regenerative feedback repeaters for programmable interconnections
    • DOBBELAERE, I., HOROWITZ, M., AND GAMAL, A. E. 1995. Regenerative feedback repeaters for programmable interconnections. IEEE J. Solid-State Circuits 30, 11 (Nov.) 1246-1253.
    • (1995) IEEE J. Solid-state Circuits , vol.30 , Issue.11 NOV , pp. 1246-1253
    • Dobbelaere, I.1    Horowitz, M.2    Gamal, A.E.3
  • 43
    • 0027837827 scopus 로고
    • A new theory of deadlock-free adaptive routing in wormhole networks
    • DUATO, J. 1993. A new theory of deadlock-free adaptive routing in wormhole networks. IEEE Trans. Parall. Distrib. Syst. 4, 12 (Dec.) 1320-1331.
    • (1993) IEEE Trans. Parall. Distrib. Syst. , vol.4 , Issue.12 DEC , pp. 1320-1331
    • Duato, J.1
  • 44
    • 0029390484 scopus 로고
    • A necessary and sufficient condition for deadlock-free adaptive routing in wormhole networks
    • DUATO, J. 1995. A necessary and sufficient condition for deadlock-free adaptive routing in wormhole networks. IEEE Trans. Parall. Distrib. Syst. 6, 10 (Oct.) 1055-1067.
    • (1995) IEEE Trans. Parall. Distrib. Syst. , vol.6 , Issue.10 OCT , pp. 1055-1067
    • Duato, J.1
  • 45
    • 0030215168 scopus 로고    scopus 로고
    • A necessary and sufficient condition for deadlock-free routing in cut-through and store-and-forward networks
    • DUATO, J. 1996. A necessary and sufficient condition for deadlock-free routing in cut-through and store-and-forward networks. IEEE Trans. Parall. Distrib. Syst. 7, 8 (Aug.) 841-854.
    • (1996) IEEE Trans. Parall. Distrib. Syst. , vol.7 , Issue.8 AUG , pp. 841-854
    • Duato, J.1
  • 46
    • 0035695821 scopus 로고    scopus 로고
    • A general theory for deadlock-free adaptive routing using a mixed set of resources
    • DUATO, J. AND PINKSTON, T. M. 2001. A general theory for deadlock-free adaptive routing using a mixed set of resources. IEEE Trans. Parall. Distrib. Syst. 12, 12 (Dec.) 1219-1235.
    • (2001) IEEE Trans. Parall. Distrib. Syst. , vol.12 , Issue.12 DEC , pp. 1219-1235
    • Duato, J.1    Pinkston, T.M.2
  • 49
    • 14844314436 scopus 로고    scopus 로고
    • An asynchronous on-chip network router with quality-of-service (QoS) support
    • IEEE
    • FELICIJAN, T. AND FURBER, S. B. 2004. An asynchronous on-chip network router with quality-of-service (QoS) support. In Proceedings IEEE International SOC Conference. IEEE, 274-277.
    • (2004) Proceedings IEEE International SOC Conference , pp. 274-277
    • Felicijan, T.1    Furber, S.B.2
  • 51
    • 0036760609 scopus 로고    scopus 로고
    • A scalable high-performance computing solution for networks on chips
    • FORSELL, M. 2002. A scalable high-performance computing solution for networks on chips. IEEE Micro 22, 5, 46-55.
    • (2002) IEEE Micro , vol.22 , Issue.5 , pp. 46-55
    • Forsell, M.1
  • 52
    • 0030170426 scopus 로고    scopus 로고
    • Distributed, deadlock-free routing in faulty, pipelined, direct interconnection networks
    • GAUGHAN, P. T., DAO, B. V., YALAMANCHILI, S., AND SCHIMMEL, D. E. 1996. Distributed, deadlock-free routing in faulty, pipelined, direct interconnection networks. IEEE Trans. Comput. 45, 6 (June) 651-665.
    • (1996) IEEE Trans. Comput. , vol.45 , Issue.6 JUNE , pp. 651-665
    • Gaughan, P.T.1    Dao, B.V.2    Yalamanchili, S.3    Schimmel, D.E.4
  • 54
    • 21644481777 scopus 로고    scopus 로고
    • Communication abstractions for system-level design and synthesis
    • Center for Embedded Computer Systems, University of California, Irvine, CA
    • GERSTLAUER, A. 2003. Communication abstractions for system-level design and synthesis. Tech. Rep. TR-03-30, Center for Embedded Computer Systems, University of California, Irvine, CA.
    • (2003) Tech. Rep. , vol.TR-03-30
    • Gerstlauer, A.1
  • 56
    • 0028513557 scopus 로고
    • The turn model for adaptive routing
    • GLASS, C. J. AND Ni, L. M. 1994. The turn model for adaptive routing. J. ACM 41, 874-902.
    • (1994) J. ACM , vol.41 , pp. 874-902
    • Glass, C.J.1    Ni, L.M.2
  • 58
    • 27344456043 scopus 로고    scopus 로고
    • Æthereal network on chip: Concepts, architectures and implementations
    • GOOSSENS, K., DIELISSEN, J., AND RADULESCU, A. 2005. Æthereal network on chip: Concepts, architectures and implementations. IEEE Design Test Comput. 22, 5, 414-421.
    • (2005) IEEE Design Test Comput. , vol.22 , Issue.5 , pp. 414-421
    • Goossens, K.1    Dielissen, J.2    Radulescu, A.3
  • 61
    • 0343825186 scopus 로고    scopus 로고
    • Contention-free communication scheduling for array redistribution
    • GUO, M., NAKATA, I., AND YAMASHITA, Y. 2000. Contention-free communication scheduling for array redistribution. Parall. Comput. 26, 1325-1343.
    • (2000) Parall. Comput. , vol.26 , pp. 1325-1343
    • Guo, M.1    Nakata, I.2    Yamashita, Y.3
  • 62
    • 27644490224 scopus 로고    scopus 로고
    • A unified approach to constrained mapping and routing on networks-on-chip architectures
    • ACM/IEEE
    • HANSSON, A., GOOSSENS, K., AND RADULESCU, A. 2005. A unified approach to constrained mapping and routing on networks-on-chip architectures. In CODES/ISSS. ACM/IEEE, 75-80.
    • (2005) CODES/ISSS , pp. 75-80
    • Hansson, A.1    Goossens, K.2    Radulescu, A.3
  • 63
    • 33750906036 scopus 로고    scopus 로고
    • Quantitative modeling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip
    • IEEE
    • HARMANCI, M., ESCUDERO, N., LEBLEBICI, Y., AND IENNE, P. 2005. Quantitative modeling and comparison of communication schemes to guarantee quality-of-service in networks-on-chip. In International Sympo-sium on Circuits and Systems (ISCAS). IEEE, 1782-1785.
    • (2005) International Sympo-sium on Circuits and Systems (ISCAS) , pp. 1782-1785
    • Harmanci, M.1    Escudero, N.2    Leblebici, Y.3    Ienne, P.4
  • 64
    • 0029191713 scopus 로고
    • Asynchronous design methodologies: An overview
    • HAUCK, S. 1995. Asynchronous design methodologies: an overview. Proceedings of the IEEE 83, 1 (Jan.) 69-93.
    • (1995) Proceedings of the IEEE , vol.83 , Issue.1 JAN , pp. 69-93
    • Hauck, S.1
  • 65
    • 33747557398 scopus 로고    scopus 로고
    • High-performance interconnects: An integration overview
    • HAVEMANN, R. H. AND HUTCHBY, J. A. 2001. High-performance interconnects: An integration overview. Proceedings of the IEEE 89, 5 (May) 586-601.
    • (2001) Proceedings of the IEEE , vol.89 , Issue.5 MAY , pp. 586-601
    • Havemann, R.H.1    Hutchby, J.A.2
  • 66
    • 84866633628 scopus 로고    scopus 로고
    • SystemC based SoC communication modeling for the OCP protocol
    • HAVERINEN, A., LECLERCQ, M., WEYRICH, N., AND WINGARD, D. 2002. SystemC based SoC communication modeling for the OCP protocol. White paper, http://www.ocpip.org.
    • (2002) White Paper
    • Haverinen, A.1    Leclercq, M.2    Weyrich, N.3    Wingard, D.4
  • 70
    • 16244389647 scopus 로고    scopus 로고
    • Application-specific buffer space allocation for networks-on-chip router design
    • IEEE/ACM
    • HU, J. AND MARCULESCU, R. 2004a. Application-specific buffer space allocation for networks-on-chip router design. In ICCAD. IEEE/ACM, 354-361.
    • (2004) ICCAD , pp. 354-361
    • Hu, J.1    Marculescu, R.2
  • 71
    • 3042658619 scopus 로고    scopus 로고
    • Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints
    • IEEE
    • HU, J. AND MARCULESCU, R. 2004b. Energy-aware communication and task scheduling for network-on-chip architectures under real-time constraints. In Proceedings of Design, Automation and Testing in Europe Conference (DATE). IEEE, 10234-10240.
    • (2004) Proceedings of Design, Automation and Testing in Europe Conference (DATE) , pp. 10234-10240
    • Hu, J.1    Marculescu, R.2
  • 72
    • 4444230968 scopus 로고    scopus 로고
    • International technology roadmap for semiconductors
    • International Technology Roadmap for Semiconductors
    • ITRS. 2001. International technology roadmap for semiconductors. Tech. rep., International Technology Roadmap for Semiconductors.
    • (2001) Tech. Rep.
  • 77
    • 0032131992 scopus 로고    scopus 로고
    • A quantitative comparison of parrallel computation models
    • JUURLINK, B. H. H. AND WIJHOFF, H. A. G. 1998. A quantitative comparison of parrallel computation models. ACM Trans. Comput. Syst. 16, 3 (Aug.) 271-318.
    • (1998) ACM Trans. Comput. Syst. , vol.16 , Issue.3 AUG , pp. 271-318
    • Juurlink, B.H.H.1    Wijhoff, H.A.G.2
  • 78
    • 0037371801 scopus 로고    scopus 로고
    • Optical interconnects for future high performance intergrated circuits
    • KAPUR, P. AND SARASWAT, K. C. 2003. Optical interconnects for future high performance intergrated circuits. Physica E 16, 3-4, 620-627.
    • (2003) Physica E , vol.16 , Issue.3-4 , pp. 620-627
    • Kapur, P.1    Saraswat, K.C.2
  • 79
    • 0036760592 scopus 로고    scopus 로고
    • An interconnect architecture for networking systems on chips
    • KARIM, F., NGUYEN, A., AND DEY, S. 2002. An interconnect architecture for networking systems on chips. IEEE Micro 22, 36-45.
    • (2002) IEEE Micro , vol.22 , pp. 36-45
    • Karim, F.1    Nguyen, A.2    Dey, S.3
  • 86
    • 0033685462 scopus 로고    scopus 로고
    • Communication architecture tuners: A methodology for the design of high-performance communication architectures for system-on-chips
    • IEEE
    • LAHIRI, K., RAGHUNATHAN, A., LAKSHMINARAYANA, G., AND DEY, S. 2000. Communication architecture tuners: A methodology for the design of high-performance communication architectures for system-on-chips. In Proceedings of the Design Automation Conference, DAC. IEEE, 513-518.
    • (2000) Proceedings of the Design Automation Conference, DAC , pp. 513-518
    • Lahiri, K.1    Raghunathan, A.2    Lakshminarayana, G.3    Dey, S.4
  • 87
    • 0009350526 scopus 로고    scopus 로고
    • On-chip interconnects - Gigahertz and beyond
    • LEE, K. 1998. On-chip interconnects - gigahertz and beyond. Solid State Technol. 41, 9 (Sept.) 85-89.
    • (1998) Solid State Technol. , vol.41 , Issue.9 SEPT , pp. 85-89
    • Lee, K.1
  • 88
    • 0022141776 scopus 로고
    • Fat-trees: Universal networks for hardware-efficient supercomputing
    • LEISERSON, C. E. 1985. Fat-trees: Universal networks for hardware-efficient supercomputing. IEEE Trans. Comput. c-34, 10, 892-901.
    • (1985) IEEE Trans. Comput. , vol.C-34 , Issue.10 , pp. 892-901
    • Leiserson, C.E.1
  • 89
    • 27644446882 scopus 로고    scopus 로고
    • Spatial division multiplexing: A novel approach for guaranteed throughput on noes
    • ACM/IEEE
    • LEROY, A., MARCHAL, P., SHICKOVA, A., CATTHOOR, F., ROBERT, F., AND VERKEST, D. 2005. Spatial division multiplexing: a novel approach for guaranteed throughput on noes. In CODES/ISSS. ACM/IEEE, 81-86.
    • (2005) CODES/ISSS , pp. 81-86
    • Leroy, A.1    Marchal, P.2    Shickova, A.3    Catthoor, F.4    Robert, F.5    Verkest, D.6
  • 90
    • 3142720340 scopus 로고    scopus 로고
    • An architecture and compiler for scalable on-chip communication
    • LIANG, J., LAFFELY, A., SRINIVASAN, S., AND TESSIER, R. 2004. An architecture and compiler for scalable on-chip communication. IEEE Trans. VLSI Syst. 12, 7, 711-726.
    • (2004) IEEE Trans. VLSI Syst. , vol.12 , Issue.7 , pp. 711-726
    • Liang, J.1    Laffely, A.2    Srinivasan, S.3    Tessier, R.4
  • 92
    • 1242309795 scopus 로고    scopus 로고
    • Interconnect intellectual property for network-on-chip (NoC)
    • LIU, J., ZHENG, L.-R., AND TENHUNEN, H. 2004. Interconnect intellectual property for network-on-chip (NoC). J. Syst. Archite. 50, 65-79.
    • (2004) J. Syst. Archite. , vol.50 , pp. 65-79
    • Liu, J.1    Zheng, L.-R.2    Tenhunen, H.3
  • 100
    • 9544237156 scopus 로고    scopus 로고
    • HERMES: An infrastructure for low area overhead packet-switching networks on chip
    • MORAES, P., CALAZANS, N., MELLO, A., MÖLLER, L., AND OST, L. 2004. HERMES: An infrastructure for low area overhead packet-switching networks on chip. The VLSI Integration 38, 69-93.
    • (2004) The VLSI Integration , vol.38 , pp. 69-93
    • Moraes, P.1    Calazans, N.2    Mello, A.3    Möller, L.4    Ost, L.5
  • 108
  • 110
    • 84858911381 scopus 로고    scopus 로고
    • The importance of sockets in SoC design
    • OCPIP. 2003a. The importance of sockets in SoC design. White paper, http://www.ocpip.org.
    • (2003) White Paper
  • 118
    • 0035101680 scopus 로고    scopus 로고
    • A delay model for router microarchitectures
    • PEH, L.-S. AND DALLY, W. J. 2001. A delay model for router microarchitectures. IEEE Micro 21, 26-34.
    • (2001) IEEE Micro , vol.21 , pp. 26-34
    • Peh, L.-S.1    Dally, W.J.2
  • 129
    • 0009563246 scopus 로고    scopus 로고
    • National technology roadmap for semiconductors 1997
    • Semiconductor Industry Association
    • SIA. 1997. National technology roadmap for semiconductors 1997. Tech. rep., Semiconductor Industry Association.
    • (1997) Tech. Rep.
  • 130
    • 9544242739 scopus 로고    scopus 로고
    • Issues in the development of a practical NoC: The Proteo concept
    • Elsevier
    • SIGUENZA-TORTOSA, D., AHONEN, T., AND NURMI, J. 2004. Issues in the development of a practical NoC: The Proteo concept. Integrat. VLSIJ. Elsevier, 95-105.
    • (2004) Integrat. VLSIJ , pp. 95-105
    • Siguenza-Tortosa, D.1    Ahonen, T.2    Nurmi, J.3
  • 140
    • 33745799807 scopus 로고    scopus 로고
    • Packet scheduling in proteo network-on-chip
    • IASTED/ACTA Press
    • TORTOSA, D. A. AND NURMI, J. 2004. Packet scheduling in proteo network-on-chip. Parall. Distrib. Comput. Netw. IASTED/ACTA Press, 116-121.
    • (2004) Parall. Distrib. Comput. Netw , pp. 116-121
    • Tortosa, D.A.1    Nurmi, J.2
  • 141
    • 0035248113 scopus 로고    scopus 로고
    • Impact of virtual channels and adaptive routing on application performance
    • VAIDYA, R. S., SIVASUBRAMANIAM, A., AND DAS, C. R. 2001. Impact of virtual channels and adaptive routing on application performance. IEEE Trans. Parall. Distrib. Syst. 12, 2 (Feb.) 223-237.
    • (2001) IEEE Trans. Parall. Distrib. Syst. , vol.12 , Issue.2 FEB , pp. 223-237
    • Vaidya, R.S.1    Sivasubramaniam, A.2    Das, C.R.3
  • 152
    • 0033704034 scopus 로고    scopus 로고
    • Low-swing on chip signaling techniques: Effectiveness and robustness
    • ZHANG, H., GEORGE, V., AND RABAEY, J. M. 1999. Low-swing on chip signaling techniques: Effectiveness and robustness. IEEE Trans. VLSI Syst. 8, 3 (Aug.) 264-272.
    • (1999) IEEE Trans. VLSI Syst. , vol.8 , Issue.3 AUG , pp. 264-272
    • Zhang, H.1    George, V.2    Rabaey, J.M.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.