-
1
-
-
0036149420
-
Networks on chips: A new SoC paradigm
-
Jan
-
L. Benini and G.D. Micheli, "Networks on chips: a new SoC paradigm," IEEE Computer, vol. 35, no. 1, pp. 70-78, Jan. 2002.
-
(2002)
IEEE Computer
, vol.35
, Issue.1
, pp. 70-78
-
-
Benini, L.1
Micheli, G.D.2
-
2
-
-
84893687806
-
A generic architecture for on-chip packetswitched interconnections
-
March
-
P. Guerrier, A. Greiner, A generic architecture for on-chip packetswitched interconnections, in: Proceedings Design and Test in Europe, March 2000, pp. 250-256.
-
(2000)
Proceedings Design and Test in Europe
, pp. 250-256
-
-
Guerrier, P.1
Greiner, A.2
-
3
-
-
0038420731
-
Design of a switch for network on chip applications
-
May
-
P.P. Pande, C. Grecu, A. Ivanov, R. Saleh, Design of a switch for network on chip applications, in: Proceedings International Symposium on Circuits and Systems (ISCAS), vol. 5, May 2003, pp. 217-220.
-
(2003)
Proceedings International Symposium on Circuits and Systems (ISCAS)
, vol.5
, pp. 217-220
-
-
Pande, P.P.1
Grecu, C.2
Ivanov, A.3
Saleh, R.4
-
4
-
-
27644469931
-
Automatic hardware-efficient SoC integration by QoS network on chip
-
December
-
E. Bolotin, A. Morgenshtein, I. Cidon, R. Ginosar, A. Kolodny, Automatic hardware-efficient SoC integration by QoS network on chip, in: Proceedings IEEE International Conference on Electronics, Circuits and Systems, December 2004, pp. 479-482.
-
(2004)
Proceedings IEEE International Conference on Electronics, Circuits and Systems
, pp. 479-482
-
-
Bolotin, E.1
Morgenshtein, A.2
Cidon, I.3
Ginosar, R.4
Kolodny, A.5
-
5
-
-
0035392176
-
Recursive diagonal torus: An interconnection network for massively parallel computers
-
Jul.
-
Y. Yang, A. Funahashi, A. Jouraku, H. Nishi, H. Amano, and T. Sueyoshi, "Recursive diagonal torus: an interconnection network for massively parallel computers," IEEE Trans. Parallel and Distributed Systems, Jul. 2001, Vol. 12, no. 7, pp. 701-715.
-
(2001)
IEEE Trans. Parallel and Distributed Systems
, vol.12
, Issue.7
, pp. 701-715
-
-
Yang, Y.1
Funahashi, A.2
Jouraku, A.3
Nishi, H.4
Amano, H.5
Sueyoshi, T.6
-
6
-
-
33846987632
-
A RDT-based interconnection network for scalable NoC designs
-
Y. Yu, M. Yang, Y. Yang, and Y. Jiang, "A RDT-based interconnection network for scalable NoC designs," Proc. IEEE ITCC, 2005, pp. 729-734.
-
(2005)
Proc. IEEE ITCC
, pp. 729-734
-
-
Yu, Y.1
Yang, M.2
Yang, Y.3
Jiang, Y.4
-
7
-
-
33846945395
-
A RDT-based interconnection network for scalable NoC designs
-
M. Yang, T. Li, Y. Jiang, and Y Yang, "A RDT-based interconnection network for scalable NoC designs," Proc. IEEE ISPAN, 2005, pp. 52-57.
-
(2005)
Proc. IEEE ISPAN
, pp. 52-57
-
-
Yang, M.1
Li, T.2
Jiang, Y.3
Yang, Y.4
-
8
-
-
34548120302
-
Topology and binary routing schemes of A PRDT-based NoC
-
Xinming Duan, Yulu Yang, Mei Yang, "Topology and Binary Routing Schemes of A PRDT-Based NoC" Proc. IEEE ITNG, 2007, pp. 920-924
-
(2007)
Proc. IEEE ITNG
, pp. 920-924
-
-
Duan, X.1
Yang, Y.2
Yang, M.3
-
9
-
-
0023346637
-
Deadlock-free message routing in multiprocessor interconnection networks
-
May
-
W.J. Dally, C.L. Seitz, "Deadlock-free message routing in multiprocessor interconnection networks," IEEE Trans. Computers, vol. 36, no. 5, pp. 547-553, May 1987.
-
(1987)
IEEE Trans. Computers
, vol.36
, Issue.5
, pp. 547-553
-
-
Dally, W.J.1
Seitz, C.L.2
-
11
-
-
0025746735
-
An adaptive and fault tolerant wormhole routingstrategy for k-ary n-cubes
-
Jan.
-
D. H. Linder and J. C. Harden, "An adaptive and fault tolerant wormhole routingstrategy for k-ary n-cubes," IEEE Transactions on Computers, C-40(1), pp. 2-12, Jan. 1991.
-
(1991)
IEEE Transactions on Computers
, vol.C-40
, Issue.1
, pp. 2-12
-
-
Linder, D.H.1
Harden, J.C.2
-
13
-
-
0027837827
-
A new theory of deadlock-free adaptive routing in wormhole networks
-
Sept
-
J. Duato, "A new theory of deadlock-free adaptive routing in wormhole networks," IEEE Trans. Parallel and Distributed Systems, vol. 4, no. 12, pp. 1320-1331, Sept. 1995.
-
(1995)
IEEE Trans. Parallel and Distributed Systems
, vol.4
, Issue.12
, pp. 1320-1331
-
-
Duato, J.1
-
14
-
-
3042565282
-
A power and performance model for network-on-chip architectures
-
N. Banerjee, P. Vellanki, and K.S. Chatha, "A power and performance model for network-on-chip architectures," Proc. Design Automation and Test in Europe (DATE2004) Conf., Vol. 2, pp. 1250-1255, 2004.
-
(2004)
Proc. Design Automation and Test in Europe (DATE2004) Conf.
, vol.2
, pp. 1250-1255
-
-
Banerjee, N.1
Vellanki, P.2
Chatha, K.S.3
|