Multi network interface architectures for fault tolerant network-on-chip

2009 International Symposium on Signals, Circuits and Systems, ISSCS 2009

Volumn , Issue , 2009, Pages

  Rantala, Ville ^a,b   Lehtonen, Teijo ^a,b   Liljeberg, Pasi ^b   Plosila, Juha ^b,c  

^a TURKU CENTRE FOR COMPUTER SCIENCE   (Finland)

^b UNIVERSITY OF TURKU   (Finland)

^c ACADEMY OF FINLAND   (Finland)

Author keywords

[No Author keywords available]

Indexed keywords

ARCHITECTURAL LEVELS; FAULT-TOLERANT NETWORKS; FAULTY LINKS; HOP COUNT; NETWORK INTERFACE; NETWORK INTERFACE ARCHITECTURE; NETWORK ON CHIP; NOC ARCHITECTURES; PROPOSED ARCHITECTURES;

ELECTRIC NETWORK TOPOLOGY; FAULT TOLERANT COMPUTER SYSTEMS; INTERFACES (COMPUTER); QUALITY ASSURANCE; ROUTERS; TELECOMMUNICATION NETWORKS;

FAULT TOLERANCE;

EID: 70449493678     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCS.2009.5206183     Document Type: Conference Paper

References (8)

1. L. Benini and G. De Micheli, "Networks on chips: a new SoC paradigm," Computer, vol.35, no.1, pp. 70-78, January 2002.
2. W. J. Dally and B. Towles, Principles and Practices of Interconnection Networks. Morgan Kaufmann, 2004.
3. M. Dehyadgari, M. Nickray, A. Afzali-kusha, and Z. Navabi, "Evaluation of pseudo adaptive XY routing using an object oriented model for NoC," in Microelectronics, 2005. ICM 2005. The 17th International Conference on, December 2005.
4. K. Kariniemi and J. Nurmi, "Fault tolerant XGFT network on chip for multi processor system on chip circuits," in Field Programmable Logic and Applications, 2005. International Conference on, August 2005, pp. 203-210.
5. T. Lehtonen, P. Liljeberg, and J. Plosila, "Fault tolerance analysis of NoC architectures," in Circuits and Systems, 2007. ISCAS 2007. IEEE International Symposium on, May 2007, pp. 361-364.
6. T. Lehtonen, V. Rantala, P. Liljeberg, and J. Plosila, "Fansi: Fault tolerant Network-on-Chip simulator," Turku Centre for Computer Science (TUCS), Tech. Rep. 935, March 2009.
7. V. Rantala, T. Lehtonen, P. Liljeberg, and J. Plosila, "Distributed traffic monitoring methods for adaptive Network-on-Chip," in NORCHIP, 2008., November 2008, pp. 233-236.
8. Z. Zhang, A. Greiner, and S. Taktak, "A reconfigurable routing algorithm for a fault-tolerant 2D-mesh Network-on-Chip," in Design Automation Conference, 2008. DAC 2008. 45th ACM/IEEE, June 2008, pp. 441-446.