Formally enhanced runtime verification to ensure NoC functional correctness

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn , Issue , 2011, Pages 410-419

  Parikh, Ritesh ^a   Bertacco, Valeria ^a  

^a UNIVERSITY OF MICHIGAN   (United States)

Author keywords

formal verification; functional correctness; network on chip; NoC; runtime verification

Indexed keywords

FORMAL VERIFICATIONS; FUNCTIONAL CORRECTNESS; NETWORK ON CHIP; NOC; RUN-TIME VERIFICATION;

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMMUNICATION; DESIGN; ERROR DETECTION; MICROPROCESSOR CHIPS; PACKET NETWORKS; SERVERS; TELECOMMUNICATION SYSTEMS; VLSI CIRCUITS;

ROUTERS;

EID: 84858787604     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/2155620.2155668     Document Type: Conference Paper

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