Defect and error tolerance in the presence of massive numbers of defects

IEEE Design and Test of Computers

Volumn 21, Issue 3, 2004, Pages 216-227

  Breuer, Melvin A ^a   Gupta, Sandeep K ^a   Mak, T M ^b  

^a University of Southern California   (United States)

^b Intel's Design Technology Group

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ERROR ANALYSIS; MICROPROCESSOR CHIPS; SPURIOUS SIGNAL NOISE; VLSI CIRCUITS;

ERROR TOLERANCE; EXTERNAL NOISE;

FAULT TOLERANT COMPUTER SYSTEMS;

EID: 3042622321     PISSN: 07407475     EISSN: None     Source Type: Journal    
DOI: 10.1109/MDT.2004.8     Document Type: Article

References (5)

1. International Technology Roadmap for Semiconductors, 2001; http://public.itrs.net/Files/2001TRS/Home.htm.
2. J. von Neumann, "Probabilistic Logic and Synthesis of Reliable Organisms from Unreliable Components," Automata Studies, C.E. Shannon and J. McCarthy, eds., Princeton Univ. Press, 1956, pp. 43-98.
3. B.W. Johnson, "Fault Tolerance," The Electrical Engineering Handbook, R.C. Dorf, ed., CRC Press, 1993, p. 2020.
4. M.A. Breuer and S.K. Gupta, "Intelligible Testing," Proc. 2nd IEEE Int'l Workshop Microprocessor Test and Verification, IEEE Press, 1999.
5. Z. Jiang and S.K. Gupta, "An ATPG for Threshold Testing: Obtaining Acceptable Yield in Future Processes," Proc. Int'l Test Conf. (ITC 02), IEEE Press, 2002, pp. 824-833.