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Analysis of error recovery schemes for networks on chips
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Murali, S.; Theocharides, T.; Vijaykrishnan, N.; Irwin, M.J.; Benini, L.; De Micheli, G.; "Analysis of error recovery schemes for networks on chips", IEEE Design & Test of Computers, Volume 22, Issue 5, Sept.-Oct. 2005, pp. 434-442.
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IEEE Design & Test of Computers
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A bottom-up approach to on-chip signal integrity
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Low power error resilient encoding for on-chip data buses
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2002. Proceedings... 4-8 March
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Bertozzi, D.; Benini, L.; De Micheli, G.; "Low power error resilient encoding for on-chip data buses", In: Design, Automation and Test in Europe Conference and Exhibition, 2002. Proceedings... pp. 102-109, 4-8 March 2002.
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Performance driven reliable link design for networks on chips
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Tamhankar, R.R.; Murali, S.; De Micheli, G.; "Performance driven reliable link design for networks on chips", In: Asia and South Pacific Design Automation Conference, 2005. Proceedings... pp. 749-754, Volume 2, 18-21 Jan. 2005.
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Networks-on-chip: The quest for on-chip fault-tolerant communication
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Error control schemes for on-chip communication links: The energy reliability tradeoff
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Bertozzi, D.; Benini, L.; De Micheli, G.; "Error control schemes for on-chip communication links: the energy reliability tradeoff, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Volume 24, Issue 6, June 2005, pp. 818-831.
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Early, accurate dependability analysis of CAN-based networked systems
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Perez, J.; Reorda, M.S.; Violante, M.; "Early, Accurate Dependability Analysis of CAN-Based Networked Systems", IEEE Design & Test of Computers, Volume 23, Issue 1, Jan. 2006.
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Fault modeling and simulation for crosstalk in system-on-chip interconnects
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1999 IEEE/ACM International conference on Computer-Aided Design, 7-11 Nov.
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Cuviello, M.; Dey, S.; Bai, X.; Zhao, Y.; "Fault modeling and simulation for crosstalk in system-on-chip interconnects", In: 1999 IEEE/ACM International conference on Computer-Aided Design. Digest of Technical Papers, pp. 297-303, 7-11 Nov. 1999.
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