TILE64™ processor: A 64-core SoC with mesh interconnect

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 51, Issue , 2008, Pages 87-89

  Bell, Shane ^a   Edwards, Bruce ^a   Amann, John ^a   Conlin, Rich ^a   Joyce, Kevin ^a   Leung, Vince ^a   MacKay, John ^a   Reif, Mike ^a   Bao, Liewei ^a   Brown, John ^a   Mattina, Matthew ^a   Miao, Chyi Chang ^a   Ramey, Carl ^a   Wentzlaff, David ^a   Anderson, Walker ^a   Berger, Ethan ^a   Fairbanks, Nat ^a   Khan, Durlov ^a   Montenegro, Froilan ^a   Stickney, Jay ^a   Zook, John ^a   more..

^a Tilera   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

MESH GENERATION; MESH NETWORKING; MULTIMEDIA SYSTEMS; PIPELINE PROCESSING SYSTEMS; PROGRAMMABLE LOGIC CONTROLLERS; VERY LONG INSTRUCTION WORD ARCHITECTURE;

90-NM CMOS; MEMORY MANAGEMENT; ON CHIPS; ON-CHIP NETWORKS;

SYSTEM-ON-CHIP;

EID: 49549108733     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISSCC.2008.4523070     Document Type: Conference Paper

References (6)

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2. J. Dorsey, S. Searles, M. Ciraula, et al., "An Integrated Quad-Core™ Opteron Processor", ISSCC Dig. Tech. Papers, pp. 102-103, Feb. 2007.
3. U. Nawathe, M. Hassan, L. Warriner, et al., "An 8-Core 64-Thread 65b Power-Efficient SPARC SoC", ISSCC Dig. Tech. Papers, pp. 108-109 Feb. 2007.
4. M. Taylor, J. Kim, J. Miller, et al., "A 16-Issue Multiple-Program-Counter Microprocessor with Point-to-Point Scalar Operand Network", ISSCC Dig. Tech. Papers, pp. 170-171, Feb. 2003.
5. S. Vangal, et al, "An 80-tile 1.28TFLOPS Network-on-Chip in 6Snm CMOS", ISSCC Dig. Tech. Papers, pp. 98, Feb. 2007.
6. A. Agarwal, L. Bao, J. Brown, et al, "Tile Processor: Embedded Multicore for Networking and Digital Multimedia", Hot Chips, Aug. 2007.