메뉴 건너뛰기




Volumn , Issue , 2010, Pages 145-154

Transient and permanent error co-management method for reliable Networks-on-Chip

Author keywords

Network on chip; Permanent error; Reliability; Spare wire; Splitting transmission; Transient error

Indexed keywords

ADAPTIVE ROUTING; CO-MANAGEMENT; CONFIGURABLE; ERROR CONDITION; ERROR CONTROL CODING; HIGH RELIABILITY; HIGH THROUGHPUT; LOW-LATENCY; NETWORK-ON-CHIP; NETWORKS ON CHIPS; NOISE CONDITIONS; PACKET LATENCIES; PERMANENT ERROR; SIMULATION RESULT; SPARE WIRE; THROUGHPUT IMPROVEMENT; TRANSIENT ERRORS;

EID: 77955112004     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/NOCS.2010.24     Document Type: Conference Paper
Times cited : (33)

References (28)
  • 3
    • 70350721965 scopus 로고    scopus 로고
    • Adaptive error control for nanometer scale NoC links
    • Nov., Special issue on advances in nanoelectronics circuits and systems
    • Q. Yu and P. Ampadu, "Adaptive error control for nanometer scale NoC links," IET Computers & Digital Techniques - Special issue on advances in nanoelectronics circuits and systems. vol. 3, no. 6, pp. 643-659, Nov. 2009.
    • (2009) IET Computers & Digital Techniques , vol.3 , Issue.6 , pp. 643-659
    • Yu, Q.1    Ampadu, P.2
  • 5
    • 34250849255 scopus 로고    scopus 로고
    • Online reconfigurable self-timed links for fault tolerant NoC
    • Article ID 94676
    • T. Lehtonen, P. Liljeberg, and J. Plosila, "Online reconfigurable self-timed links for fault tolerant NoC," VLSI Design, vol. 2007, Article ID 94676, pp. 1-13, 2007.
    • (2007) VLSI Design , vol.2007 , pp. 1-13
    • Lehtonen, T.1    Liljeberg, P.2    Plosila, J.3
  • 9
    • 69949106800 scopus 로고    scopus 로고
    • LTR: A low-overhead and reliable routing algorithm for Network on Chips
    • Nov.
    • A. Patooghy and S. G. Miremadi, "LTR: A low-overhead and reliable routing algorithm for Network on Chips," in Proc. Intl. SoC Design Conf., pp. 129-133, Nov. 2008.
    • (2008) Proc. Intl. SoC Design Conf. , pp. 129-133
    • Patooghy, A.1    Miremadi, S.G.2
  • 11
    • 0141837018 scopus 로고    scopus 로고
    • Trends and challenges in VLSI circuit reliability
    • Jul./Aug.
    • C. Constantinescu, "Trends and challenges in VLSI circuit reliability," IEEE Micro, vol. 23, no.4, pp. 14-19, Jul./Aug.2003.
    • (2003) IEEE Micro , vol.23 , Issue.4 , pp. 14-19
    • Constantinescu, C.1
  • 12
    • 84942033424 scopus 로고    scopus 로고
    • Networks-on-chip: The quest for on-chip fault-tolerant communication
    • Feb.
    • R. Mǎrculescu, "Networks-on-chip: The quest for on-chip fault-tolerant communication," in Proc. IEEE Annula Symp. on VLSI (ISVLSI'03), pp. 8-12, Feb. 2003.
    • (2003) Proc. IEEE Annula Symp. on VLSI (ISVLSI'03) , pp. 8-12
    • Mǎrculescu, R.1
  • 13
    • 34548476457 scopus 로고    scopus 로고
    • Crosstalk fault modeling in defective pair of interconnects
    • Jan.
    • A. K. Palit, K. K. Duganapallia and W. Anheiera, "Crosstalk fault modeling in defective pair of interconnects," Integration, the VLSI Journal, vol. 41, no. 1, pp. 27-37, Jan. 2008.
    • (2008) Integration, the VLSI Journal , vol.41 , Issue.1 , pp. 27-37
    • Palit, A.K.1    Duganapallia, K.K.2    Anheiera, W.3
  • 14
    • 40949110161 scopus 로고    scopus 로고
    • Design of low power & reliable networks on chip through joint crosstalk avoidance and multiple error correction coding
    • Jan.
    • A. Ganguly, P. P. Pande, B. Belzer and C. Grecu, "Design of Low Power & Reliable Networks on Chip through Joint Crosstalk Avoidance and Multiple Error Correction Coding," J. Electronic Testing, vol. 24, no. 1, pp. 67-81, Jan. 2008.
    • (2008) J. Electronic Testing , vol.24 , Issue.1 , pp. 67-81
    • Ganguly, A.1    Pande, P.P.2    Belzer, B.3    Grecu, C.4
  • 17
    • 27344448860 scopus 로고    scopus 로고
    • Analysis of error recovery schemes for networks on chips
    • Sept.-Oct.
    • S. Murali, L. Benini, M. J. Irwin and G. De Micheli, "Analysis of Error Recovery Schemes for Networks on Chips," IEEE Design & Test of Computer, vol. 22, no. 5, pp. 434-442, Sept.-Oct. 2005.
    • (2005) IEEE Design & Test of Computer , vol.22 , Issue.5 , pp. 434-442
    • Murali, S.1    Benini, L.2    Irwin, M.J.3    De Micheli, G.4
  • 18
    • 70349257426 scopus 로고    scopus 로고
    • On hamming product codes with type-II hybrid ARQ for on-chip interconnects
    • Sept.
    • B. Fu and P. Ampadu, "On hamming product codes with type-II hybrid ARQ for on-chip interconnects," IEEE Trans. on Circuits and Syst. I, vol. 56, no. 9, pp. 2042-2054, Sept. 2009.
    • (2009) IEEE Trans. on Circuits and Syst. I , vol.56 , Issue.9 , pp. 2042-2054
    • Fu, B.1    Ampadu, P.2
  • 19
    • 1142287741 scopus 로고    scopus 로고
    • A fault model notation and error-control scheme for switch-to-switch buses in a Network-on-Chip
    • Oct.
    • H. Zimmer and A. Jantsch, "A fault model notation and error-control scheme for switch-to-switch buses in a Network-on-Chip," in Proc. CODES+ISSS'03, pp. 188-193, Oct. 2003.
    • (2003) Proc. CODES+ISSS'03 , pp. 188-193
    • Zimmer, H.1    Jantsch, A.2
  • 21
    • 34548130068 scopus 로고    scopus 로고
    • A fault tolerant mechanism for handling permanent and transient failures in a network on chip
    • Apr.
    • M. Ali, M. Welzl and S. Hessler, "A fault tolerant mechanism for handling permanent and transient failures in a network on chip," in Proc. Intl. Conf. on Info. Technology (ITNG'07), pp. 1027-1032, Apr. 2007.
    • (2007) Proc. Intl. Conf. on Info. Technology (ITNG'07) , pp. 1027-1032
    • Ali, M.1    Welzl, M.2    Hessler, S.3
  • 26
    • 0033873392 scopus 로고    scopus 로고
    • Modeling of interconnect capacitance, delay, and crosstalk in VLSI
    • Feb.
    • S. Wong, G. Lee, D. Ma, "Modeling of interconnect capacitance, delay, and crosstalk in VLSI," IEEE Tran. Semiconductor Manufacturing, vol. 13, no. 1, pp. 108-111, Feb. 2000.
    • (2000) IEEE Tran. Semiconductor Manufacturing , vol.13 , Issue.1 , pp. 108-111
    • Wong, S.1    Lee, G.2    Ma, D.3
  • 27
    • 4243681615 scopus 로고    scopus 로고
    • Online, Available
    • Arizona State University, Predictive Technology Model [Online]. Available: http://www.eas.asu.edu/~ptm.
    • Predictive Technology Model


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.