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A network on chip architecture and design methodology
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April
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S. Kumar, A. Jantsch, J.P. Soininen, M. Forsell, M. Millberg, J. Oberg, K. Tiensyrja and A. Hemani, "A network on chip architecture and design methodology", IEEE Computer Society Annual Symposium on VLSI, pp. 117-122, April 2002.
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IEEE Computer Society Annual Symposium on VLSI
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Kumar, S.1
Jantsch, A.2
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Millberg, M.5
Oberg, J.6
Tiensyrja, K.7
Hemani, A.8
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2
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Evaluation of on-chip networks using deflection routing
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GLSVLSI'06 - Proceedings of the 2006 ACM Great Lakes Symposium on VLSI
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Z. Lu, M. Zhong, and A. Jantsch, "Evaluation of on-chip networks using deflection routing", ACM Great Lakes symposium on VLSI, pp. 296-301, May 2006. (Pubitemid 44729263)
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Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI
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Lu, Z.1
Zhong, M.2
Jantsch, A.3
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3
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Fault-tolerant architecture and deflection routing for degradable NoC switches
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May
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A. Kohler and M. Radetzki, "Fault-tolerant architecture and deflection routing for degradable NoC switches", IEEE International Symposium on Networks-on-Chip, pp. 22-31, May 2009.
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IEEE International Symposium on Networks-on-Chip
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Kohler, A.1
Radetzki, M.2
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4
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Towards on-chip fault-tolerant communication
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January
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T. Dumitras, S. Kerner, and R. Marculescu, "Towards on-chip fault-tolerant communication", Asia and South Pacific Design Automation Conference, pp. 225-232, January 2003.
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Asia and South Pacific Design Automation Conference
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Dumitras, T.1
Kerner, S.2
Marculescu, R.3
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5
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Fault tolerant algorithms for Network-on-Chip interconnect
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February
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M. Pirretti, G.M. Link, A.R. Brooks, N. Vijaykrishnan, M. Kandemir and M.J. Irwin, "Fault tolerant algorithms for Network-on-Chip interconnect", IEEE Computer Society Annual Symposium on VLSI, pp. 46-51 ,February 2004.
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IEEE Computer Society Annual Symposium on VLSI
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Pirretti, M.1
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Brooks, A.R.3
Vijaykrishnan, N.4
Kandemir, M.5
Irwin, M.J.6
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6
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Fully adaptive fault-tolerant routing algorithm for Network-on-Chip architectures
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August
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T. Schonwald, J. Zimmermann, O. Bringmann and W. Rosenstiel, "Fully adaptive fault-tolerant routing algorithm for Network-on-Chip architectures", Euromicro Conference on Digital System Design Architectures, Methods and Tools, pp. 527-534, August 2007.
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Euromicro Conference on Digital System Design Architectures, Methods and Tools
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Schonwald, T.1
Zimmermann, J.2
Bringmann, O.3
Rosenstiel, W.4
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7
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51549089448
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A reconfigurable routing algorithm for a fault-tolerant 2D-mesh Network-on-Chip
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June
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Z. Zhang, A. Greiner and S. Taktak, "A reconfigurable routing algorithm for a fault-tolerant 2D-mesh Network-on-Chip", ACMIIEEE Design Automation Conference, pp. 441-446, June 2008.
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ACMIIEEE Design Automation Conference
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Zhang, Z.1
Greiner, A.2
Taktak, S.3
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8
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A highly resilient routing algorithm for fault-tolerant NoCs
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April
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D. Fick, A. DeOrio, G. Chen, V. Bertacco, D. Sylvester and D. Blaauw, "A highly resilient routing algorithm for fault-tolerant NoCs", Design, Automation & Test in Europe Conference & Exhibition, pp.21-26, April 2009.
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Design, Automation & Test in Europe Conference & Exhibition
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Fick, D.1
Deorio, A.2
Chen, G.3
Bertacco, V.4
Sylvester, D.5
Blaauw, D.6
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9
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Load distribution with the proximity congestion awareness in a network on chip
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March
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E. Nilsson, M. Millberg, J. Oberg and A. Jantsch, "Load distribution with the proximity congestion awareness in a network on chip", Design, Automation & Test in Europe Conference & Exhibition, pp.1126-1127, March 2003.
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Design, Automation & Test in Europe Conference & Exhibition
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Nilsson, E.1
Millberg, M.2
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Jantsch, A.4
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10
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TDM virtual-circuit configuration for network-on-chip
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August
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Z. Lu and A. Jantsch, "TDM Virtual-Circuit Configuration for Network-on-Chip", IEEE Transaction on VLSI Systems, Vol. 16, No.8, pp. 1021-1034, August 2008.
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IEEE Transaction on VLSI Systems
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Lu, Z.1
Jantsch, A.2
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11
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0033750124
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Softwarebased rerouting for fault-tolerant pipelined communication
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March
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Y.J. Suh, B.V. Dao, J. Duato and S. Yalamanchili, "Softwarebased rerouting for fault-tolerant pipelined communication", IEEE Transaction on Parallel and Distributed Systems, Vol. 11, No. 3, pp. 193-211, March 2000.
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IEEE Transaction on Parallel and Distributed Systems
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Suh, Y.J.1
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